Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
☆58Jun 23, 2021Updated 4 years ago
Alternatives and similar repositories for ZYNQ_ADC_DMA_LWIP
Users that are interested in ZYNQ_ADC_DMA_LWIP are comparing it to the libraries listed below
Sorting:
- LiteX based FPGA gateware for Thunderscope.☆28Updated this week
- PYNQ-Z1 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx☆12Jun 16, 2021Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆61Oct 20, 2022Updated 3 years ago
- 利用ZYNQ7020实现SAR数据采集系统，其中包含硬件设计代码、上位机、测试程序。☆14Feb 27, 2025Updated last year
- Open Source iMX6 Rex module design files in Cadence. More at:☆24Aug 2, 2018Updated 7 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆12Jan 21, 2022Updated 4 years ago
- ZYNQ-7000 based data transfer through TCP/IP protocol☆12Apr 20, 2023Updated 2 years ago
- Use FPGA to Transfer Image with Gigabits Ethernet☆19Dec 2, 2020Updated 5 years ago
- This project is basically ultrasound Beamformer prototype and FPGA is used to control all the modules of the Hardware.☆15Nov 9, 2017Updated 8 years ago
- An 8-layer board in Kicad built upon Xilinx Zynq Chip. Includes sound output, HDMI, DDR3, and Arduino Uno style header for screen connect…☆68Nov 6, 2021Updated 4 years ago
- 基于USB2.0 的数据采集卡☆21Feb 20, 2019Updated 7 years ago
- Gamma-spectroscopy of (irradiated) samples in Python☆21Mar 6, 2024Updated last year
- Real-time GPU Beamformer for DSA110 written in C/CUDA☆22May 21, 2019Updated 6 years ago
- An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.☆51Nov 23, 2013Updated 12 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆56Apr 27, 2017Updated 8 years ago
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 6 years ago
- DVI to LVDS Verilog converter☆25Sep 3, 2016Updated 9 years ago
- Digital FM Radio Receiver for FPGA☆66Dec 26, 2015Updated 10 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆29Mar 24, 2021Updated 4 years ago
- UDP-IP stack accelerator and is able to send and receive data through Ethernet link☆44Nov 3, 2025Updated 4 months ago
- Periodica is a Beautiful yet extremely useful and intuitive Periodic Table representation.☆11Jul 20, 2022Updated 3 years ago
- easy-peasy optimal flight trajectory☆38Feb 20, 2026Updated last week
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆33Aug 7, 2021Updated 4 years ago
- TCL scripts for FPGA (Xilinx)☆35Jul 5, 2022Updated 3 years ago
- ☆12Aug 25, 2022Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆78Apr 11, 2022Updated 3 years ago
- 基于verilog实现了ISP图像处理IP☆316Nov 28, 2022Updated 3 years ago
- 基于ZYNQ+AD9363的开源SDR硬件☆559Sep 13, 2022Updated 3 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆36Jun 7, 2022Updated 3 years ago
- I2S transciever implemented in Verilog HDL☆32Oct 11, 2017Updated 8 years ago
- VHDL codes to generate GPS L1 C/A and Galileo E1OS and E5 PRNs and dataless signals. Secondary codes not included.☆32Feb 22, 2019Updated 7 years ago
- Application software for Scopy MVP: FPGA PS, PL, and microcontroller firmware☆79Nov 28, 2020Updated 5 years ago
- ☆12Nov 8, 2025Updated 3 months ago
- ☆11Apr 3, 2017Updated 8 years ago
- ☆38Mar 26, 2017Updated 8 years ago
- gqrx-Hamlib interface with GUI☆12Apr 29, 2018Updated 7 years ago
- Detecting Radiological Threats in Urban Areas (9th place solution)☆10May 4, 2019Updated 6 years ago
- High-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆10Jul 12, 2020Updated 5 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago