Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
☆62Jun 23, 2021Updated 5 years ago
Alternatives and similar repositories for ZYNQ_ADC_DMA_LWIP
Users that are interested in ZYNQ_ADC_DMA_LWIP are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- EBAZ4205 and AD9226 as a 0-32 MHz radio spectrum viewer☆16Dec 8, 2022Updated 3 years ago
- 利用ZYNQ7020实现SAR数据采集系统，其中包含硬件设计代码、上位机、测试程序。☆14Feb 27, 2025Updated last year
- UDP and TCP echo servers using lwIP RAW API running on Xilinx Zynq Platform☆12Apr 15, 2014Updated 12 years ago
- LiteX based FPGA gateware for Thunderscope.☆30Apr 21, 2026Updated 2 months ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆30Mar 24, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An 8-layer board in Kicad built upon Xilinx Zynq Chip. Includes sound output, HDMI, DDR3, and Arduino Uno style header for screen connect…☆73Nov 6, 2021Updated 4 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆14Jan 21, 2022Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆68Oct 20, 2022Updated 3 years ago
- minimal code to access ps DDR from PL☆23Oct 18, 2019Updated 6 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆57Apr 27, 2017Updated 9 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆46Jun 7, 2017Updated 9 years ago
- I2S transciever implemented in Verilog HDL☆34Oct 11, 2017Updated 8 years ago
- LWDO-SDR - experimental LF/VLF SDR timing receiver☆16May 13, 2022Updated 4 years ago
- This project is basically ultrasound Beamformer prototype and FPGA is used to control all the modules of the Hardware.☆16Nov 9, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Nov 17, 2021Updated 4 years ago
- 包含AD5686R的电路原理图、PCB，以及对AD5684、AD5685、AD5686兼容的驱动程序☆21Aug 17, 2021Updated 4 years ago
- 基于USB2.0 的数据采集卡☆21Feb 20, 2019Updated 7 years ago
- Wishbone SATA Controller☆26Jun 23, 2026Updated last week
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆83Apr 11, 2022Updated 4 years ago
- Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.☆40Apr 4, 2026Updated 3 months ago
- DVI to LVDS Verilog converter☆25Sep 3, 2016Updated 9 years ago
- Experimental DRM+/FM decoder☆26Mar 16, 2022Updated 4 years ago
- ☆19Sep 14, 2025Updated 9 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 🙌 Low-cost 2D ultrasound imaging hardware for makers☆41Dec 9, 2018Updated 7 years ago
- 提供一份稍完整的xduts参考示例，供西电学子入门xduts使用☆42Apr 17, 2024Updated 2 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆61Jun 23, 2026Updated last week
- WinUSB implementation for the ZYNQ platform (Zybo board)☆28Aug 27, 2018Updated 7 years ago
- Demo FreeRTOS project targeting stm32 with LCD☆11May 6, 2014Updated 12 years ago
- Ethernet MAC 10/100 Mbps☆88Oct 2, 2019Updated 6 years ago
- UDP-IP stack accelerator and is able to send and receive data through Ethernet link☆48Nov 3, 2025Updated 8 months ago
- Smart Grid State Estimation with PMUs TimeSynchronization Errors☆14Dec 1, 2020Updated 5 years ago
- Project framework for data scalable 7-bit CPU with stack architecture☆10Jan 22, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Dual-Channel, Low Noise, Modular, 100 kHz Bandwidth, 24-Bit Data Acquisition (DAQ) Device / FFT Signal Analyzer☆15Sep 26, 2022Updated 3 years ago
- SAR Backprojection Implementations for the GOTCHA data set☆15Jan 28, 2024Updated 2 years ago
- Real-time GPU Beamformer for DSA110 written in C/CUDA☆25May 21, 2019Updated 7 years ago
- 软件无线电，使用FPGA进行正交解调。☆23Feb 18, 2019Updated 7 years ago
- 基于ZYNQ+AD9363的开源SDR硬件☆593Sep 13, 2022Updated 3 years ago
- This repository contains codes and texts related with the FPGA RTL Implementation of the Delay and Sum Beamformer☆22Apr 4, 2022Updated 4 years ago
- The FreePMU project delivers an open source Phasor Measurement Unit (PMU) for power system analysis based on the STM32F769 Discovery kit …☆14Aug 25, 2022Updated 3 years ago