Alternatives and similar repositories for TDC

Users that are interested in TDC are comparing it to the libraries listed below

• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆66Updated 10 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆69Updated 4 years ago
• jobisoft / jTDC
  FPGA based 30ps RMS TDCs
  ☆89Updated 7 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆60Updated 3 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆53Updated 4 years ago
• shinde-shantanu / FPGA_TDC
  Time to Digital Converter on an FPGA
  ☆15Updated 5 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆31Updated 6 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆73Updated 3 years ago
• marsohod4you / FpgaTDC
  Project: Precise Measure of time delays in FPGA
  ☆30Updated 8 years ago
• VideoGPU / MIPI_CSI2_TX
  VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes
  ☆76Updated 2 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆217Updated last year
• LGG1997 / FPGA_TDC_1_0
  ☆12Updated 3 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆62Updated 3 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆314Updated 2 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆114Updated last year
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆80Updated 6 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆53Updated 11 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆89Updated 7 years ago
• gonzagab / tdc
  A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
  ☆23Updated 8 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 13 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• charkster / spi_slave_verilog
  SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
  ☆17Updated 6 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆62Updated 9 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆54Updated last month
• csus-senior-design / i2c
  I2C Master and Slave
  ☆37Updated 10 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• GOOD-Stuff / srio_test
  Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)
  ☆18Updated 8 years ago