Alternatives and similar repositories for TDC:

Users that are interested in TDC are comparing it to the libraries listed below

• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆60Updated 10 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆59Updated 3 years ago
• marsohod4you / FpgaTDC
  Project: Precise Measure of time delays in FPGA
  ☆29Updated 7 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆49Updated 2 years ago
• gonzagab / tdc
  A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
  ☆21Updated 7 years ago
• shinde-shantanu / FPGA_TDC
  Time to Digital Converter on an FPGA
  ☆14Updated 4 years ago
• jobisoft / jTDC
  FPGA based 30ps RMS TDCs
  ☆84Updated 7 years ago
• LGG1997 / FPGA_TDC_1_0
  ☆10Updated 2 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆30Updated 5 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆46Updated 3 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆70Updated 2 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• PranavGovekar / tdcOnFPGA
  Implementation of tappped delay line TDC on FPGA
  ☆13Updated 2 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆53Updated 3 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆33Updated 9 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆65Updated 3 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆22Updated 5 years ago
• suisuisi / 8b10b_encdec
  8b10b Encoder/Decoder
  ☆11Updated 10 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆44Updated 3 weeks ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆35Updated 3 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆37Updated 3 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆31Updated 4 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆53Updated 9 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆15Updated 6 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆66Updated 7 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• charkster / spi_slave_verilog
  SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
  ☆15Updated 5 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆55Updated 8 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆75Updated 5 years ago