RuiMachado39 / TDCLinks
Verilog implementation of a tapped delay line TDC
☆46Updated 7 years ago
Alternatives and similar repositories for TDC
Users that are interested in TDC are comparing it to the libraries listed below
Sorting:
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆68Updated 11 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆71Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆62Updated 3 years ago
- FPGA based 30ps RMS TDCs☆91Updated 7 years ago
- Time to Digital Converter on an FPGA☆18Updated 5 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- USB 2.0 Device IP Core☆74Updated 8 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆58Updated 4 years ago
- ☆34Updated 6 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆76Updated 2 years ago
- Project: Precise Measure of time delays in FPGA☆30Updated 8 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆64Updated 3 years ago
- I2C Master and Slave☆38Updated 10 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆116Updated 2 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆20Updated 6 years ago
- configurable cordic core in verilog☆53Updated 11 years ago
- ☆12Updated 3 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- SPI Slave for FPGA in Verilog and VHDL☆220Updated last year
- Verilog SPI master and slave☆62Updated 10 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆84Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago