madamic / zynq_tdc
A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
☆57Updated 3 years ago
Alternatives and similar repositories for zynq_tdc:
Users that are interested in zynq_tdc are comparing it to the libraries listed below
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆60Updated 10 years ago
- Verilog implementation of a tapped delay line TDC☆39Updated 6 years ago
- Time to Digital Converter on an FPGA☆14Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- FPGA based 30ps RMS TDCs☆82Updated 7 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆30Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆103Updated last year
- All digital PLL☆28Updated 7 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆44Updated 3 years ago
- Board repo for the ZCU216 RFSOC☆25Updated 2 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆88Updated 6 years ago
- ☆10Updated 2 years ago
- Project: Precise Measure of time delays in FPGA☆29Updated 7 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆48Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆54Updated 2 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆44Updated 3 years ago
- Verilog digital signal processing components☆129Updated 2 years ago
- A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.☆20Updated 7 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆69Updated 2 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Updated 2 years ago
- Python productivity for RFSoC platforms☆65Updated 10 months ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆58Updated 4 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆76Updated 8 months ago
- Single Port RAM, Dual Port RAM, FIFO☆22Updated 2 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆23Updated last year
- Interface Protocol in Verilog☆49Updated 5 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆62Updated 2 years ago