Alternatives and similar repositories for zynq_tdc:

Users that are interested in zynq_tdc are comparing it to the libraries listed below

• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆59Updated 10 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆49Updated 2 years ago
• RuiMachado39 / TDC
  Verilog implementation of a tapped delay line TDC
  ☆38Updated 6 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆101Updated last year
• shinde-shantanu / FPGA_TDC
  Time to Digital Converter on an FPGA
  ☆14Updated 4 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆31Updated 3 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆30Updated 4 years ago
• filipamator / adpll
  All digital PLL
  ☆27Updated 7 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆27Updated 2 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆42Updated 3 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆67Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆126Updated 2 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆52Updated 2 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆88Updated 6 years ago
• jobisoft / jTDC
  FPGA based 30ps RMS TDCs
  ☆82Updated 6 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆33Updated 10 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• Xilinx / RFSoC-MTS
  A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).
  ☆23Updated last year
• farbius / dsp_xilinx_ip
  Some basic DSP algorithms implemented with xilinx IP cores with explanation, Verilog testbenches and modelling in Python
  ☆33Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆65Updated 2 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆42Updated 3 years ago
• gonzagab / tdc
  A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
  ☆20Updated 7 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆57Updated last year
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆47Updated 2 years ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆45Updated last year
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆25Updated 2 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆93Updated 4 years ago
• marsohod4you / FpgaTDC
  Project: Precise Measure of time delays in FPGA
  ☆28Updated 7 years ago