nkrackow / SingularitySurfer-FPGA-Lock-In-Amplifier
Repository for the development of an FPGA based DSP Lock-In Amplifier
☆62Updated last year
Alternatives and similar repositories for SingularitySurfer-FPGA-Lock-In-Amplifier:
Users that are interested in SingularitySurfer-FPGA-Lock-In-Amplifier are comparing it to the libraries listed below
- FPGA Based lock in amplifier☆33Updated last year
- migen + misoc + redpitaya = digital servo☆37Updated 6 years ago
- AMC module with Xilinx RF-SoC and two analog front-end mezzanines for SDR and quantum applications☆39Updated 2 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆57Updated 3 years ago
- This is a open source hardware (and software) RF Signal Generator using readily available off the shelf-components.☆11Updated 5 years ago
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆60Updated 10 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆20Updated 9 years ago
- NIST digital servo: an FPGA based fast digital feedback controller☆70Updated 7 years ago
- A Time to Digital Converter designed for Xilinx 7-Series FPGAs☆25Updated 4 years ago
- A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.☆20Updated 7 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆30Updated 4 years ago
- SDK for FPGA / Linux Instruments☆99Updated 2 weeks ago
- FPGA-Based DIY Function Generator☆51Updated 4 years ago
- FPGA based 30ps RMS TDCs☆83Updated 7 years ago
- Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya☆39Updated 10 months ago
- Safe and compact low power high voltage controller for piezoelectric actuators☆32Updated 7 years ago
- Repository for FPGA projects☆49Updated 5 months ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- Lock-in and PID application for RedPitaya enviroment☆47Updated 2 years ago
- Serial communication link bit error rate tester simulator, written in Python.☆104Updated 5 months ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆61Updated 2 years ago
- Verilog implementation of a tapped delay line TDC☆39Updated 6 years ago
- Time to Digital Converter on an FPGA☆14Updated 4 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆43Updated 3 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- Transform the Red Pitaya in an acquisition card☆29Updated 3 years ago
- ☆14Updated 8 years ago
- RF electronics engineering ecosystem☆25Updated 2 years ago
- ☆30Updated 4 years ago
- Collections of guides and projects related to testing RedPitaya☆52Updated 5 years ago