shinde-shantanu / FPGA_TDC

Related projects: ⓘ

• gonzagab / tdc
  A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
  ☆19Updated 7 years ago
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆56Updated 9 years ago
• RuiMachado39 / TDC
  Verilog implementation of a tapped delay line TDC
  ☆35Updated 5 years ago
• marsohod4you / FpgaTDC
  Project: Precise Measure of time delays in FPGA
  ☆25Updated 7 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆47Updated 3 years ago
• jobisoft / jTDC
  FPGA based 30ps RMS TDCs
  ☆75Updated 6 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆25Updated 3 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆44Updated last year
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆65Updated 2 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆29Updated 4 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 4 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆28Updated 5 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆17Updated 12 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆38Updated 2 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆47Updated 5 years ago
• QuantumQuadrate / HamamatsuCameralink
  FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.
  ☆18Updated 8 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆49Updated 2 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆34Updated 3 years ago
• benbr8 / tdc-fpga
  A Time to Digital Converter designed for Xilinx 7-Series FPGAs
  ☆20Updated 3 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆38Updated 9 months ago
• DeamonYang / FPGA_SYNC_ASYNC_FIFO
  FPGA 同步FIFO与异步FIFO
  ☆28Updated 5 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆28Updated 9 years ago
• freecores / uart2spi
  UART To SPI
  ☆15Updated 10 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆22Updated 5 years ago
• BigPig-Bro / Cyclone-IV
  【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板
  ☆16Updated 9 months ago
• FilMarini / FPGA_CDR_core
  FPGA implementation of a CDR targeting a Xilinx Kintex-7 for data rates up to 250 MHz
  ☆14Updated 2 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 2 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆40Updated 2 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆23Updated 2 years ago
• C-Aniruddh / 8bit_sar_adc
  Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC
  ☆20Updated 6 years ago