PaserTech-Hardware / GowinDDR3_AXI4_SpinalHDL

Related projects ⓘ

Alternatives and complementary repositories for GowinDDR3_AXI4_SpinalHDL

• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆37Updated 4 months ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆35Updated 3 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆47Updated last year
• open-dv / dma_axi
  ☆16Updated 5 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 4 years ago
• rbarzic / ml-ahb-gen
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆12Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆33Updated 2 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 4 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆17Updated 5 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆52Updated 7 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆34Updated 9 years ago
• mahmutefil / AXI2APB-Bridge-Design-and-Verification
  In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…
  ☆13Updated 2 years ago
• caicaicai-ji / QSPI_FOR_SOC
  QSPI for SoC
  ☆16Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆56Updated 10 months ago
• SpinalHDL / SpinalDoc-RTD
  The sources of the online SpinalHDL doc
  ☆25Updated this week
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 3 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆50Updated 10 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• balanx / SpinalHDLDemo
  Demo Sources for Learning Spinal HDL
  ☆13Updated last year
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆47Updated 5 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆39Updated 11 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆58Updated 2 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆16Updated 4 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆20Updated 2 months ago
• BigPig-Bro / Cyclone-IV
  【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板
  ☆17Updated 11 months ago
• briansune / Kintex-7-OV13850-Verilog
  kintex7 ov13850 fpga mipi camera
  ☆17Updated 9 months ago
• zhutmost / edgeboard
  Make Baidu EdgeBoard Lite as a general Zynq FPGA development board
  ☆23Updated last year
• mballance / clusterv-soc
  Quad cluster of RISC-V cores with peripherals and local memory
  ☆22Updated 2 years ago