☆11Dec 3, 2025Updated 11 months ago
Alternatives and similar repositories for microwatt_design_challenge
Users that are interested in microwatt_design_challenge are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated last year
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 8 months ago
- 24bit CPU with integrated GPU made in Logisim☆15Mar 3, 2026Updated 8 months ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆21Jul 28, 2025Updated last year
- ☆10May 30, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An analog circuit topology benchmark for LLMs☆17Jun 23, 2026Updated 4 months ago
- ☆23May 12, 2026Updated 5 months ago
- Ride the Wellen! 🌊☆17Aug 27, 2026Updated 2 months ago
- Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Da…☆30Updated this week
- ARCH hardware description language and compiler☆79Updated this week
- A minimal neuromorphic chip design in SystemVerilog to learn how brain-inspired computing works from the ground up.☆29Mar 30, 2026Updated 7 months ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆67Nov 7, 2024Updated last year
- ☆29Mar 8, 2026Updated 7 months ago
- CVA6 softcore contest☆25Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- HLS for Networks-on-Chip☆40Feb 18, 2021Updated 5 years ago
- Verilog interface for HC-SR04 Ultrasonic Ranging Module☆10Aug 3, 2023Updated 3 years ago
- A button blinky for stm32 which doesn't use RAM and fits under 50 bytes.☆13Sep 7, 2025Updated last year
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆35Feb 24, 2026Updated 8 months ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- ☆17Jun 5, 2024Updated 2 years ago
- Projects with Software Defined Radio (SDR) for Computer Networks Class☆17Dec 1, 2020Updated 5 years ago
- The VE-HEP RTL and Firmware☆12Mar 19, 2024Updated 2 years ago
- Lightweight Llama 3 8B Inference Engine in CUDA C☆52Mar 21, 2025Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆53Jul 11, 2025Updated last year
- ☆14Aug 8, 2026Updated 2 months ago
- A fixed function pipeline GPU☆40Mar 18, 2026Updated 7 months ago
- A ROHD-based framework for connectivity and assembly of hardware designs.☆14Sep 9, 2026Updated last month
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆42Jul 30, 2026Updated 3 months ago
- mWATTBAT: The open source Radar Chip☆12Sep 1, 2025Updated last year
- Custom IC Design Platform☆124Updated this week
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- ☆13Jun 10, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- ☆16Mar 17, 2026Updated 7 months ago
- ☆11Mar 22, 2022Updated 4 years ago
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆229Jun 5, 2026Updated 4 months ago
- A short and on point tutorial on how to use an ASIC logic synthesis tool☆17Jul 3, 2026Updated 4 months ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 10 years ago
- ☆21Oct 8, 2026Updated 3 weeks ago