irajPatel / irajPatel_RISC-V-SoC-Tapeout-Program_VSDView on GitHub
In this program, we learn to design a System-on-Chip (SoC) from basic RTL to GDSII using open-source tools. Part of India’s largest collaborative RISC-V tapeout initiative, empowering 3500+ participants to build silicon and advance the nation’s semiconductor ecosystem.
☆10Nov 25, 2025Updated 11 months ago

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