Full custom IC design, layout, and post-layout verification of a 9-bit differential Successive Approximation Register (SAR) ADC in TSMC 65nm, featuring a Razavi-style bootstrapped sampling network. Taped out as part of a 6-group collaborative top chip.
☆19Oct 4, 2026Updated last month
Alternatives and similar repositories for 9-bit-SAR-ADC
Users that are interested in 9-bit-SAR-ADC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source CFET standard-cell PDK with backside power delivery and CFlex track-mixing libraries for RTL-to-GDS DTCO.☆14Oct 21, 2026Updated 3 weeks ago
- NEORV32 RISC-V SoC running Zephyr RTOS on FPGA bare metal - with an extensible accelerator pipeline architecture, including an DMA-enable…☆18Aug 16, 2026Updated 2 months ago
- ☆14Jun 10, 2026Updated 5 months ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 8 months ago
- TinyWhisper: An Open-Source Fully-Integrated Multi-Mode Short-Wave Transmitter for Amateur Radio Applications in 130-nm CMOS☆27Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AnalogStudio is a comprehensive, professional-grade Electronic Design Automation (EDA) software suite developed by Algo Science Lab for d…☆21Jul 22, 2026Updated 3 months ago
- A simple motion extraction for video inspired from posy☆12Aug 13, 2024Updated 2 years ago
- ☆48Oct 25, 2026Updated 2 weeks ago
- ☆16May 8, 2018Updated 8 years ago
- Interactive 3D Layout Viewer for GDSII☆20Jun 14, 2024Updated 2 years ago
- [ICML 2023] Official code for "DevFormer: A Symmetric Transformer for Context-Aware Device Placement"☆23Dec 7, 2024Updated last year
- snp2le: A PySide6 Interactive GUI and CLI-based S-Parameter to Lumped-Element Netlist Converter☆12Nov 4, 2026Updated last week
- A Python tool that compiles neural network weights directly into synthesizable Verilog for the ASIC toolchain.☆15Sep 3, 2026Updated 2 months ago
- SAR ADC design knowledge base for agentic IC design: architecture, CDAC, comparator, bootstrap, async logic, integration, and Spectre ver…☆19Apr 5, 2026Updated 7 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆36Updated this week
- In this program, we learn to design a System-on-Chip (SoC) from basic RTL to GDSII using open-source tools. Part of India’s largest colla…☆10Nov 25, 2025Updated 11 months ago
- An auto compounding bot for the iron.finance private vaults☆25Feb 26, 2024Updated 2 years ago
- Testfield: T593☆15Apr 27, 2026Updated 6 months ago
- This project discusses the design procedure of a Low Dropout Voltage Regulator (LDO) circuit.☆34Feb 28, 2024Updated 2 years ago
- Advanced Integrated Circuits 2026☆17Oct 9, 2026Updated last month
- Programming (8051)☆11Nov 23, 2018Updated 7 years ago
- Verilog interface for HC-SR04 Ultrasonic Ranging Module☆10Aug 3, 2023Updated 3 years ago
- ☆18Sep 7, 2026Updated 2 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A button blinky for stm32 which doesn't use RAM and fits under 50 bytes.☆13Sep 7, 2025Updated last year
- ☆22Updated this week
- Projects with Software Defined Radio (SDR) for Computer Networks Class☆17Dec 1, 2020Updated 5 years ago
- ☆22Updated this week
- ☆11Dec 3, 2025Updated 11 months ago
- Unified RISC-V Prefetch Queue and Branch Predictor☆11Sep 21, 2026Updated last month
- A short and on point tutorial on how to use an ASIC logic synthesis tool☆17Jul 3, 2026Updated 4 months ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- CXLMemUring: A Hardware Software Co-design Paradigm for Asynchronous and Flexible Parallel CXL Memory Pool Access☆13Sep 13, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆27Updated this week
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆142Feb 22, 2024Updated 2 years ago
- This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…☆14May 6, 2020Updated 6 years ago
- ☆16Mar 17, 2026Updated 7 months ago
- A standalone, FP4-quantized General Matrix Multiply (GEMM) core, from RTL through synthesis and full place-and-route in the OpenLane 2 fl…☆11May 22, 2026Updated 5 months ago
- ☆14Aug 8, 2026Updated 3 months ago
- ☆17Oct 13, 2024Updated 2 years ago
Are these results useful?