Alternatives and similar repositories for langproc-cw:

Users that are interested in langproc-cw are comparing it to the libraries listed below

• clemenkok / IAC0
  The Missing Gaps
  ☆9Updated last year
• EIE2-IAC-Labs / Project_Brief
  ☆1Updated 5 months ago
• ADimoska / SOMASExtended
  ☆8Updated 4 months ago
• Aaron-Zhao123 / ELEC50009
  Course material for ELEC50009
  ☆16Updated 3 months ago
• johnwickerson / HSV
  ☆29Updated 4 months ago
• edstott / EEE1labs
  ☆30Updated last month
• DeepWok / mase
  Machine-Learning Accelerator System Exploration Tools
  ☆158Updated this week
• edstott / EEE2Rover
  Updated last year
• chrisneuf / Deep-Neural-Network-Hardware-Accelerator
  My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
  ☆27Updated 5 years ago
• tms4517 / 2D-Systolic-Array-Multiplier
  2D Systolic Array Multiplier
  ☆13Updated last year
• milestone12 / JSON.sv
  SystemVerilog package for reading, manipulating, and writing JSON-formatted data
  ☆10Updated 3 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆129Updated 5 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆44Updated 9 months ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆149Updated 10 months ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆98Updated 4 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆50Updated 4 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆167Updated this week
• bol-edu / 2022-fall-ntu
  ☆32Updated 7 months ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆90Updated 5 months ago
• raysalemi / Python4RTLVerification
  ☆154Updated 2 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆58Updated last year
• nxbyte / Verilog-Projects
  This repository contains source code for past labs and projects involving FPGA and Verilog based designs
  ☆108Updated 5 years ago
• muditbhargava66 / High-Frequency-Trading-FPGA-System
  The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, orde…
  ☆93Updated last year
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆51Updated last year
• simon-staal / Odyssey_C_Compiler
  This repository contains the preprocessed C90 to MIPS assembly compiler produced as part of the EIE 2nd Year Instruction Set Architecture…
  ☆18Updated 2 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆76Updated 2 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆75Updated last year
• MPSLab-ASU / ML-Accelerators
  Topics in Machine Learning Accelerator Design
  ☆72Updated 2 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆38Updated 2 years ago
• georgeyhere / FPGA-Video-Processing
  Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
  ☆25Updated 3 years ago