Alternatives and similar repositories for ELEC50009

Users that are interested in ELEC50009 are comparing it to the libraries listed below

• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆166Updated 3 months ago
• Xilinx / Vivado-Design-Tutorials
  ☆221Updated last month
• accellera-official / uvm-core
  ☆94Updated last year
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆103Updated 10 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆453Updated 2 months ago
• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆26Updated 5 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆52Updated last year
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆139Updated 3 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆450Updated last month
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆390Updated last year
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆133Updated 5 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆354Updated last week
• RV-BOSC / OpenNoC
  ☆187Updated 2 months ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆82Updated 3 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆278Updated last year
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆362Updated 2 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆213Updated this week
• Xilinx / XilinxBoardStore
  ☆292Updated 2 weeks ago
• raysalemi / Python4RTLVerification
  ☆164Updated 2 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆164Updated 5 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆90Updated 6 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆217Updated 2 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆152Updated last year
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆72Updated last year
• ahmad-mirsalari / PULP
  A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.
  ☆27Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆173Updated this week
• bol-edu / caravel-soc_fpga-lab
  ☆19Updated 4 months ago
• ytliu74 / RISCV_Verilog
  RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.
  ☆19Updated 2 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆670Updated 2 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆160Updated last year