Aaron-Zhao123 / ELEC50009
Course material for ELEC50009
☆11Updated 9 months ago
Related projects ⓘ
Alternatives and complementary repositories for ELEC50009
- ☆26Updated last week
- An Open-Source Tool for CGRA Accelerators☆17Updated 7 months ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- An overview of TL-Verilog resources and projects☆72Updated 8 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆118Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆39Updated 4 years ago
- SystemVerilog Tutorial☆114Updated 11 months ago
- SystemVerilog synthesis tool☆169Updated this week
- ☆38Updated last year
- Code used in☆174Updated 7 years ago
- ☆14Updated last month
- ☆38Updated 2 months ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆13Updated 9 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆20Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆135Updated last year
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆11Updated last year
- Verilog Implementation of 32-bit Floating Point Adder☆32Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆36Updated 4 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆65Updated 3 months ago
- Computer-aided VLSI System design, EEE 5022, National Taiwan University, 2018 Spring☆16Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- Introductory course into static timing analysis (STA).☆66Updated 2 weeks ago
- DRA+RISC-V Exploration Framework☆16Updated 10 months ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 6 years ago
- This repo provide an index of VLSI content creators and their materials☆136Updated 3 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- ☆26Updated 5 years ago