simon-staal / Odyssey_C_Compiler

Related projects: ⓘ

• Aaron-Zhao123 / ELEC50009
  Course material for ELEC50009
  ☆11Updated 7 months ago
• OliverKillane / Imperial-Computing-Notes
  A selection of textbook-like course notes for the Imperial College Computing modules.
  ☆55Updated 5 months ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆111Updated 9 months ago
• MatchLab-Imperial / machine-learning-course
  ☆10Updated last year
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆129Updated last month
• efabless / chipcraft---mest-course
  ☆28Updated 3 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆42Updated last year
• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆15Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆78Updated 5 months ago
• kcelebi / riscv-assembler
  RISC-V Assembly code assembler package for Python.
  ☆51Updated last year
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆48Updated last week
• janestreet / hardcaml
  Hardcaml is an OCaml library for designing hardware.
  ☆646Updated 3 weeks ago
• m8pple / elec50010-2020-verilog-lab
  Verilog lab material for ELEC50010 class
  ☆10Updated 3 years ago
• jieltan / OpenCompArchCourse
  ☆17Updated 3 years ago
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆49Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆43Updated 8 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆165Updated 2 years ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆24Updated 9 months ago
• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆12Updated last month
• karimmahmoud22 / SystemVerilog-For-Verification
  ☆18Updated 4 months ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆31Updated 4 years ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆142Updated 3 years ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆117Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆26Updated 2 months ago
• FPGADude / Digital-Design
  Verilog HDL files
  ☆83Updated 3 months ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆38Updated last month
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆10Updated 2 years ago
• ARC-Lab-UF / intel-training-modules
  ☆38Updated last year
• chipsalliance / synlig
  SystemVerilog support for Yosys
  ☆156Updated this week
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆217Updated last week