simon-staal / Odyssey_C_CompilerLinks
This repository contains the preprocessed C90 to MIPS assembly compiler produced as part of the EIE 2nd Year Instruction Set Architecture and Compilers coursework.
☆18Updated 2 years ago
Alternatives and similar repositories for Odyssey_C_Compiler
Users that are interested in Odyssey_C_Compiler are comparing it to the libraries listed below
Sorting:
- Course material for ELEC50009☆16Updated 5 months ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆583Updated this week
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆17Updated 6 months ago
- ☆15Updated 2 years ago
- ☆1Updated 7 months ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,108Updated this week
- Verilog implementation of multi-stage 32-bit RISC-V processor☆115Updated 4 years ago
- Magic VLSI Layout Tool☆554Updated last month
- ☆29Updated 2 months ago
- 100 Days of RTL☆383Updated 11 months ago
- Verilog evaluation benchmark for large language model☆292Updated this week
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆361Updated 2 months ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,533Updated last week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆303Updated 4 months ago
- ECE 3300 HDL Code☆51Updated 2 years ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆462Updated this week
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆394Updated this week
- ☆20Updated 6 months ago
- synthesiseable ieee 754 floating point library in verilog☆658Updated 2 years ago
- Top-level files and pin assignment scripts for various Altera FPGAs☆12Updated 8 years ago
- 16 bit CPU created in Vivado with Verilog☆18Updated 3 years ago
- Installs Vivado on M1/M2/M3 macs☆444Updated 9 months ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆726Updated last year
- Modular hardware build system☆1,049Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆574Updated this week
- cadence flow for genus and innovus with UPF added.☆11Updated 4 years ago
- This repo provide an index of VLSI content creators and their materials☆152Updated 10 months ago
- A vision transformer based framework for classifying executable images as benign or malicious☆9Updated last year
- Training Neural Networks using Analog circuits☆22Updated 4 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆444Updated 4 months ago