Alternatives and similar repositories for Odyssey_C_Compiler:

Users that are interested in Odyssey_C_Compiler are comparing it to the libraries listed below

• edstott / ES-CW1
  ☆14Updated last month
• johnwickerson / HSV
  ☆28Updated 3 months ago
• Aaron-Zhao123 / ELEC50009
  Course material for ELEC50009
  ☆16Updated last month
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆144Updated 6 months ago
• clemenkok / IAC0
  The Missing Gaps
  ☆9Updated last year
• LangProc / langproc-cw
  Compiler coursework repository for Instruction Architectures and Compilers module at Imperial College London
  ☆20Updated last week
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆77Updated 9 years ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆107Updated last week
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆128Updated last week
• EIE2-IAC-Labs / Project_Brief
  ☆1Updated 3 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆66Updated last year
• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆23Updated 4 years ago
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆53Updated 2 years ago
• ahirsharan / 32-Bit-Floating-Point-Adder
  Verilog Implementation of 32-bit Floating Point Adder
  ☆36Updated 4 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆38Updated 8 months ago
• FPGADude / Digital-Design
  Verilog HDL files
  ☆125Updated 9 months ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆38Updated last year
• lin-e / imperial-revision
  ☆17Updated 3 years ago
• cathalmccabe / PYNQ_tutorials
  ☆79Updated last year
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆48Updated 4 years ago
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆307Updated 5 months ago
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆15Updated 2 months ago
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆25Updated 7 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆41Updated 4 years ago
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆41Updated 7 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆98Updated 10 months ago
• aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
  This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…
  ☆15Updated 3 years ago
• jieltan / OpenCompArchCourse
  ☆21Updated 3 years ago