simon-staal / Odyssey_C_CompilerLinks
This repository contains the preprocessed C90 to MIPS assembly compiler produced as part of the EIE 2nd Year Instruction Set Architecture and Compilers coursework.
☆18Updated 2 years ago
Alternatives and similar repositories for Odyssey_C_Compiler
Users that are interested in Odyssey_C_Compiler are comparing it to the libraries listed below
Sorting:
- Lab Coursework Signals and Systems☆12Updated 2 weeks ago
- Design of a 16-Bit CPU using Verilog☆40Updated 6 years ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆24Updated 9 months ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆400Updated 3 months ago
- This project aims to implement a pipelined processor based on the RISC-V instruction set architecture (ISA) using Vivado and Verilog. The…☆17Updated last year
- ECE 3300 HDL Code☆58Updated 2 years ago
- A roadmap for those who want to build a career as an FPGA / ASIC Engineer☆424Updated 10 months ago
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆36Updated 5 years ago
- Verilog HDL files☆153Updated last year
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆24Updated 2 years ago
- 100 Days of RTL☆399Updated last year
- Open source tools for IC design☆13Updated 10 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆273Updated 4 months ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- SystemVerilog Tutorial☆176Updated last week
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆96Updated 2 years ago
- Verilog Project☆16Updated 4 years ago
- This repo provide an index of VLSI content creators and their materials☆158Updated last year
- ☆42Updated 2 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆119Updated 3 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆53Updated last year
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆29Updated 2 months ago
- lowRISC Style Guides☆460Updated 4 months ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆19Updated 4 years ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆678Updated this week
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆22Updated last year
- ☆86Updated last month
- ☆15Updated 2 years ago
- ☆117Updated last year
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆41Updated last year