Alternatives and similar repositories for LA_EMU:

Users that are interested in LA_EMU are comparing it to the libraries listed below

• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆17Updated last month
• JamesAslan / MicroArchBench
  ☆69Updated 5 months ago
• cogbt / COGBT
  Compile Optimization Guided Binary Translator (using llvm as infrastructure)
  ☆47Updated 8 months ago
• xuefeng16 / Tyche-Artifact
  [TACO 2024] A hardware prefetching framework employing Tyche, a hardware prefetcher designed for indirect memory access patterns.
  ☆21Updated last year
• jaypiper / simulator
  ☆27Updated this week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆48Updated 5 months ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆55Updated 2 weeks ago
• jiegec / unofficial-loongarch-intrinsics-guide
  Unofficial LoongArch Intrinsics Guide
  ☆51Updated 3 weeks ago
• rrwhx / runspec
  替代spec官方的runspec脚本，可以运行在spec的命令前加上前缀命令，用于收集各种信息
  ☆11Updated last month
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆37Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• LoongsonLab / loongsonlab.github.io
  ☆11Updated 9 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated last week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 8 months ago
• Siudya / Nanhu
  Open-source high-performance RISC-V processor
  ☆29Updated last month
• OpenXiangShan / GEM5
  ☆80Updated this week
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆20Updated 2 months ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆116Updated 5 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆60Updated 2 years ago
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆21Updated 8 months ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆38Updated 2 months ago
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆59Updated last year
• OSCPU / openperf
  ☆11Updated 2 months ago
• ysyx-org / jemu-decoder
  The decoder library for jemu execution and web documentation
  ☆54Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆152Updated 6 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆61Updated last year