rrwhx / LA_EMULinks
Loongarch Emulator
☆19Updated 7 months ago
Alternatives and similar repositories for LA_EMU
Users that are interested in LA_EMU are comparing it to the libraries listed below
Sorting:
- ☆74Updated 11 months ago
- CPU micro benchmarks☆62Updated 4 months ago
- Xiangshan deterministic workloads generator☆22Updated 5 months ago
- [TACO 2024] A hardware prefetching framework employing Tyche, a hardware prefetcher designed for indirect memory access patterns.☆24Updated last year
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆117Updated 11 months ago
- ☆58Updated 2 weeks ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆32Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- ☆17Updated 3 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated last month
- Compile Optimization Guided Binary Translator (using llvm as infrastructure)☆52Updated last year
- A Study of the SiFive Inclusive L2 Cache☆67Updated last year
- Documentation for XiangShan Design☆35Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last week
- Modern co-simulation framework for RISC-V CPUs☆159Updated last week
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆55Updated 4 years ago
- RISC-V architecture concurrency model litmus tests☆89Updated 4 months ago
- ☆104Updated last week
- Super fast RISC-V ISA emulator for XiangShan processor☆295Updated last week
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- The decoder library for jemu execution and web documentation☆54Updated 2 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆42Updated last year
- PCIe Device Emulation in QEMU☆81Updated 2 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆22Updated last month
- Open-source high-performance RISC-V processor☆31Updated 4 months ago
- ☆22Updated 2 years ago