Alternatives and similar repositories for iob-uart:

Users that are interested in iob-uart are comparing it to the libraries listed below

• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• AlSaqr-platform / he-soc
  ☆32Updated this week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆103Updated 4 months ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆45Updated 5 months ago
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆35Updated 2 weeks ago
• IObundle / iob-mem
  Verilog behavioral description of various memories
  ☆30Updated 2 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆28Updated last month
• hukenovs / tcl_for_fpga
  TCL scripts for FPGA (Xilinx)
  ☆31Updated 2 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆139Updated 3 months ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• pulp-platform / hyperbus
  ☆21Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆40Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆42Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆68Updated last week
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆4Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• riscv-software-src / riscv-isac
  ☆32Updated 2 months ago
• RoaLogic / ahb3lite_memory
  Multi-Technology RAM with AHB3Lite interface
  ☆21Updated 8 months ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆24Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 3 years ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆32Updated 2 weeks ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆11Updated 10 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 8 months ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆30Updated last year