fixstars / ultra96_design

Related projects ⓘ

Alternatives and complementary repositories for ultra96_design

• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 4 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆25Updated 3 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆29Updated 3 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆128Updated last year
• Xilinx / Xilinx_Kria_KV260_Workshop
  ☆40Updated 3 years ago
• nikkatsa7 / HOG_Zedboard
  A real time Histogram of Oriented Gradients Implementation on FPGA
  ☆30Updated 6 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• parimalp / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆18Updated 6 years ago
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• Digilent / Zybo-Z7-20-pcam-5c
  ☆53Updated 2 years ago
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆17Updated 7 years ago
• Digilent / Petalinux-Zybo-Z7-20
  ☆52Updated 2 years ago
• pulp-platform / pulp-dsp
  ☆32Updated last year
• ryuz / jelly
  Original FPGA platform
  ☆51Updated last week
• pulp-platform / ne16
  Neural Engine, 16 input channels
  ☆13Updated 2 years ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆59Updated last month
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆39Updated 7 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆58Updated 2 months ago
• andrewandrepowell / zybo_petalinux_video_hls
  Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.
  ☆25Updated 8 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆67Updated 2 years ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 6 years ago
• Xilinx / GO-PYNQ
  Xilinx Contest Kshitij 2019
  ☆19Updated last year
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 5 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆19Updated 6 years ago
• ikwzm / fclkcfg
  FPGA Clock Configuration Device Driver for Linux
  ☆26Updated last year
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆15Updated last year
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆52Updated 8 years ago
• sfox14 / pynq-ekf
  A multi-board Extended Kalman Filter (EKF)
  ☆28Updated 6 years ago