rits-drsl / ZybotR2-96-fpt19
An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
☆17Updated 4 years ago
Related projects: ⓘ
- 10G Ethernet MAC implementation☆21Updated 4 years ago
- Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.☆26Updated 3 years ago
- HOG + SVM on FPGA☆25Updated 3 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 5 years ago
- ☆13Updated 6 years ago
- Basic Common Modules☆34Updated 2 months ago
- Implementation VexRiscv on ultra96☆10Updated 2 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Updated 4 years ago
- Original FPGA platform☆50Updated last week
- みんなのSystemVerilog☆19Updated 2 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Updated 4 months ago
- autonomous driving contest reference kit☆10Updated 2 years ago
- Open design rule (1um)☆17Updated last year
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆51Updated 7 years ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆43Updated 3 years ago
- Zynq PR Management☆11Updated 8 years ago
- Binary Neural Network Framework for FPGA(Differentiable LUT)☆136Updated last month
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆99Updated 2 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆101Updated 2 weeks ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆54Updated 4 years ago
- RISC-V RV32IMAFC Core for MCU☆34Updated 2 weeks ago
- Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems☆22Updated 3 years ago
- PYNQ-Z1 board files for Vivado☆32Updated 2 years ago
- ☆81Updated 3 months ago
- PYNQ support and examples for Kria SOMs☆89Updated last month
- Virtual Platform for AWS FPGA support☆15Updated 5 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆32Updated 6 years ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆125Updated last year
- PYNQ with Chisel and Rust☆24Updated 6 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆38Updated 2 years ago