Alternatives and similar repositories for ZybotR2-96-fpt19:

Users that are interested in ZybotR2-96-fpt19 are comparing it to the libraries listed below

• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• HirokiNakahara / FPGA_lecture
  Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
  ☆26Updated 3 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆26Updated 4 years ago
• ryuz / jelly
  Original FPGA platform
  ☆61Updated this week
• fixstars / ultra96_design
  Repository of HW design and SW for Ultra96 board + MIPI board
  ☆17Updated 6 years ago
• lp6m / VexRiscv_Ultra96
  Implementation VexRiscv on ultra96
  ☆12Updated 2 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆37Updated 3 months ago
• fpga-design-contest / ad-refkit
  autonomous driving contest reference kit
  ☆10Updated 3 years ago
• kazuyamashi / cReComp
  ☆13Updated 6 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆103Updated last month
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 2 years ago
• MakeLSI / OpenRule1um
  Open design rule (1um)
  ☆18Updated 2 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆154Updated 4 months ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated 10 months ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆103Updated 3 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 4 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆36Updated last month
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 8 months ago
• icgrp / prflow_nested_dfx
  Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
  ☆13Updated last year
• Digilent / Petalinux-Zybo-Z7-20
  ☆53Updated 2 years ago
• Xilinx / logicnets
  ☆87Updated 9 months ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• HirokiNakahara / FPGA_AI_Edge_Contest_2019
  Sample scripts for FPGA-based AI Edge Contest 2019
  ☆11Updated 5 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆52Updated 8 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆60Updated 5 years ago
• Edgecortix-Inc / mera
  A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix
  ☆33Updated 7 months ago