This project demonstrates DSP capabilities of Terasic DE2-115
☆29Jun 22, 2018Updated 8 years ago
Alternatives and similar repositories for FFTVisualizer
Users that are interested in FFTVisualizer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆76Apr 24, 2020Updated 6 years ago
- PID controller on an FPGA with custom RS232 addressing protocol.☆26Sep 7, 2021Updated 4 years ago
- A CIC filter implemented in Verilog☆25Sep 7, 2015Updated 10 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Audio DSP on an FPGA using eurorack-pmod + LiteX with firmware in Rust.☆17Oct 7, 2025Updated 9 months ago
- Student project for using audio on the DE2-115 FPGA development board.☆28Apr 28, 2018Updated 8 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 11 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆16Nov 12, 2025Updated 7 months ago
- A small and flexible MPD client that may act as standalone application for an audio system.☆11Apr 17, 2023Updated 3 years ago
- S/PDIF receiver with support of compressed formats☆10Dec 8, 2024Updated last year
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 11 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- Fusesoc compatible rtl cores☆18Nov 23, 2022Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆13Mar 21, 2024Updated 2 years ago
- An incomplete port of Darknet (and YOLO) to the Qualcomm Snapdragon 820 processor using the Symphony System Manager SDK to better utilize…☆13Apr 5, 2017Updated 9 years ago
- Sample code for "Reflections on trusting trust" by Ken Thompson☆15May 19, 2018Updated 8 years ago
- Template project for LiteX-based SoCs☆22May 20, 2026Updated last month
- FIR implemention with Verilog☆50May 18, 2019Updated 7 years ago
- ☆23Feb 15, 2023Updated 3 years ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- Verilog module for calculation of FFT.☆194Aug 22, 2012Updated 13 years ago
- This repository contains files and instructions requred to build and use ShadowTac, an high resolution vision based tactile sensor.☆13Sep 18, 2025Updated 9 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Mandelbrot Set in VHDL targetting the Cyclone IVE found on a DE2-115 board.☆11May 2, 2013Updated 13 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆15Mar 23, 2022Updated 4 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32May 6, 2017Updated 9 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆57May 10, 2021Updated 5 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 6 years ago
- Files and libraries belonging to the getting started guide "Serial communication with the freeDSP"☆11Apr 14, 2016Updated 10 years ago
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 6 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆35Aug 7, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- SysY is a subset of the C programming language. It's a language used in Huawei Bisheng Compiler System Design Contest☆16Oct 7, 2021Updated 4 years ago
- A Single-path Delay Feedback FFT Generator☆15Mar 20, 2024Updated 2 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated 2 months ago
- This repository includes code to convert an image to a 3-color-image in order to display it on an E-ink display.☆13Aug 27, 2019Updated 6 years ago
- ☆11Jul 26, 2017Updated 8 years ago
- Python + Octave code for measuring surface height using fringe deflectometry. Probably not useful to anyone else at this point.☆11Jan 6, 2014Updated 12 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆33Mar 13, 2025Updated last year