Goshik92 / FFTVisualizerLinks
This project demonstrates DSP capabilities of Terasic DE2-115
☆26Updated 7 years ago
Alternatives and similar repositories for FFTVisualizer
Users that are interested in FFTVisualizer are comparing it to the libraries listed below
Sorting:
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- Audio controller (I2S, SPDIF, DAC)☆86Updated 5 years ago
- Verilog modules required to get the OV7670 camera working☆72Updated 7 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆85Updated 2 years ago
- A series of CORDIC related projects☆110Updated 9 months ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆53Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆59Updated 4 years ago
- VHDL Modules☆24Updated 10 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆41Updated 3 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆62Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 6 years ago
- development interface mil-std-1553b for system on chip☆22Updated 7 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆116Updated 4 years ago
- Verilog SPI master and slave☆57Updated 9 years ago
- An i2c master controller implemented in Verilog☆31Updated 8 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- The CORDIC algorithm implemented in Octave/MATLAB and Verilog☆31Updated 10 years ago
- An CAN bus Controller implemented in Verilog☆48Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆28Updated 2 years ago
- Simple UART controller for FPGA written in VHDL☆100Updated 4 years ago
- 8051 core☆106Updated 11 years ago
- SPI Master Core clone from OpenCores☆11Updated 11 years ago