merledu / symbiflow-magic
This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
☆10Updated 3 years ago
Alternatives and similar repositories for symbiflow-magic
Users that are interested in symbiflow-magic are comparing it to the libraries listed below
Sorting:
- understanding the tinyfpga bootloader☆24Updated 7 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆18Updated 2 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 2 months ago
- A collection of SPI related cores☆17Updated 6 months ago
- PLEASE MOVE TO PAWSv2☆17Updated 3 years ago
- Yosys Plugins☆21Updated 5 years ago
- A padring generator for ASICs☆25Updated last year
- nMigen examples for the ULX3S board☆16Updated 4 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆29Updated 2 years ago
- A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC☆14Updated 5 years ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- crap-o-scope scope implementation for icestick☆20Updated 6 years ago
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated last week
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Use ECP5 JTAG port to interact with user design☆26Updated 3 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Löwe FPGA Board☆12Updated last year
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 4 years ago
- Mini CPU design with JTAG UART support☆20Updated 3 years ago
- a small simple slow serial FPGA core☆16Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year