Alternatives and similar repositories for ece_4305

Users that are interested in ece_4305 are comparing it to the libraries listed below

• Xilinx / Vivado-Design-Tutorials
  ☆221Updated last month
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆166Updated 3 months ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆152Updated last year
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆160Updated last year
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆390Updated last year
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆265Updated 3 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆453Updated 2 months ago
• aseddin / ece_3300
  ECE 3300 HDL Code
  ☆58Updated 2 years ago
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆215Updated 3 months ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆141Updated 3 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆143Updated 4 years ago
• raysalemi / Python4RTLVerification
  ☆164Updated 2 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆114Updated 3 months ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆141Updated 11 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆372Updated last year
• accellera-official / uvm-core
  ☆94Updated last year
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆93Updated 2 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆44Updated 6 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆90Updated 6 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆157Updated last year
• matbi86 / 01_ai_accelerator_basic_for_student
  ai_accelerator_basic_for_student (no solve)
  ☆12Updated 5 years ago
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆32Updated 8 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆199Updated 8 years ago
• Xilinx / PYNQ_Workshop
  ☆444Updated 11 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆450Updated last month
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆33Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆107Updated 2 years ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆102Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆278Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆120Updated 4 years ago