NEORV32 RISC-V SoC running Zephyr RTOS on FPGA bare metal - with an extensible accelerator pipeline architecture, including an DMA-enabled programmable spectral filter pipeline - wrapped in C++20 HAL from fabric to std::span.
☆18Aug 16, 2026Updated 2 months ago
Alternatives and similar repositories for Ostomachion
Users that are interested in Ostomachion are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆18Sep 7, 2026Updated 2 months ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 8 months ago
- openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and…☆28Updated this week
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆42Jul 30, 2026Updated 3 months ago
- ☆14Aug 8, 2026Updated 3 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Full custom IC design, layout, and post-layout verification of a 9-bit differential Successive Approximation Register (SAR) ADC in TSMC 6…☆19Oct 4, 2026Updated last month
- A PCIe RTL implementation☆27Aug 16, 2026Updated 2 months ago
- ☆14Jun 10, 2026Updated 5 months ago
- PSOC SoC code with peripherals and synthesis scripts for FPGA/ASIC☆12Oct 8, 2025Updated last year
- Unified RISC-V Prefetch Queue and Branch Predictor☆11Sep 21, 2026Updated last month
- Tightly Coupled Bus, low complexity, high performance system bus.☆13Updated this week
- A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication☆47Jul 13, 2026Updated 3 months ago
- ☆64Sep 4, 2026Updated 2 months ago
- OpenLayout: an open-source custom IC design environment (KLayout, xschem, ngspice, FasterCap). ASAP7 today, support for more PDKs coming.☆22Nov 4, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆10Oct 1, 2026Updated last month
- ☆72Jul 13, 2026Updated 3 months ago
- The SoC for the introduction to chip design course spring 2026☆21May 22, 2026Updated 5 months ago
- In this program, we learn to design a System-on-Chip (SoC) from basic RTL to GDSII using open-source tools. Part of India’s largest colla…☆10Nov 25, 2025Updated 11 months ago
- IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator tape…☆44Jul 10, 2026Updated 4 months ago
- SystemVerilog file list pruner☆19Oct 19, 2026Updated 3 weeks ago
- Minimal Ada VT100 API library. [when one doesn't need full ncurses...]☆12Jul 2, 2015Updated 11 years ago
- ☆25Aug 9, 2026Updated 3 months ago
- A screen recorder for modern Linux desktops (Wayland & X11), via xdg-desktop-portal + PipeWire.☆17Sep 4, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Computer Architecture: A Quantitative Approach in SystemVerilog / VHDL☆43Updated this week
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Oct 2, 2026Updated last month
- Verilog interface for HC-SR04 Ultrasonic Ranging Module☆10Aug 3, 2023Updated 3 years ago
- A button blinky for stm32 which doesn't use RAM and fits under 50 bytes.☆13Sep 7, 2025Updated last year
- This project discusses the design procedure of a Low Dropout Voltage Regulator (LDO) circuit.☆34Feb 28, 2024Updated 2 years ago
- Box3D physics engine converted to Q48.16 fixed-point math: uniform 1/65536 resolution across a ±1.4e14 meter world with stable equilibriu…☆23Updated this week
- Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, AXI, and AXI-St…☆19Updated this week
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆28Jan 24, 2026Updated 9 months ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Projects with Software Defined Radio (SDR) for Computer Networks Class☆17Dec 1, 2020Updated 5 years ago
- A fast, open-source DRC (Design Rule Check) engine for GDSII layouts.☆63Updated this week
- ☆18Sep 15, 2026Updated last month
- ☆13Updated this week
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆29Aug 12, 2026Updated 3 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆42Feb 24, 2025Updated last year
- ☆11Dec 3, 2025Updated 11 months ago
Are these results useful?