Cloneless1 is an open-source tamper-resistant cryptographic ASIC design
☆27Jul 30, 2026Updated 2 months ago
Alternatives and similar repositories for Cloneless1
Users that are interested in Cloneless1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HeiChips 2025 LibreLane Workshop☆18Aug 25, 2025Updated last year
- Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, AXI, and AXI-St…☆18Sep 6, 2026Updated 3 weeks ago
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆27Aug 12, 2026Updated last month
- Self-contained RTL to GDS flow for simple chip designs☆76Jul 7, 2026Updated 2 months ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆18Sep 10, 2026Updated 3 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆40Sep 10, 2026Updated 3 weeks ago
- Virtual development board for HDL design☆44Mar 31, 2023Updated 3 years ago
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆25Sep 21, 2026Updated 2 weeks ago
- Generate symbols from HDL components/modules☆23Feb 6, 2023Updated 3 years ago
- Open-source PDK version manager☆67Sep 19, 2026Updated 2 weeks ago
- Specification of the Wishbone SoC Interconnect Architecture☆54Jun 5, 2022Updated 4 years ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 7 months ago
- A tiny FABulous FPGA for TTIHP26a☆15Apr 9, 2026Updated 5 months ago
- Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - analog, mixed signal and custom GDS projects☆19Sep 15, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A novel Design-for-Test flow using LibreLane☆48May 9, 2026Updated 4 months ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Project template for wafer.space MPW runs using the gf180mcu PDK☆53Aug 12, 2026Updated last month
- A KiCad Plugin for Drawing PCB Tracks in Spiral Shape☆18Mar 5, 2026Updated 7 months ago
- A Chip Design Automation Solution with Open Source EDA Tools.☆32Updated this week
- Interface definitions for VHDL-2019.☆36May 13, 2026Updated 4 months ago
- End-to-End Open-Source I2C GPIO Expander☆45Sep 24, 2026Updated last week
- A Risc-V SoC for Tiny Tapeout☆61Jul 12, 2026Updated 2 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Evidence profiles for AI-generated RTL that expose what functional benchmarks miss. Seeking collaborators, design partners, and validatio…☆21Sep 28, 2026Updated last week
- Blender GDSII Importer with PDK Support☆140Updated this week
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆38Mar 28, 2026Updated 6 months ago
- ☆20Aug 25, 2026Updated last month
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI☆75Sep 22, 2026Updated last week
- Hardware Description Language Translator☆19Aug 7, 2026Updated last month
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 6 years ago
- A tapeout-ready structure for hierarchical analog design (v0.1).☆26Jan 16, 2026Updated 8 months ago
- is a comprehensive, cross-platform standalone application built for modern Analog IC Designers. It streamlines the $g_m/I_D$ design metho…☆19Apr 2, 2026Updated 6 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆18Dec 24, 2020Updated 5 years ago
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆35Updated this week
- Port of ciccreator to Python☆23Updated this week
- Tiny Tapeout project build tools + chip integration scripts☆36Sep 21, 2026Updated 2 weeks ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆19Nov 16, 2023Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆123Sep 22, 2026Updated last week
- ☆67Mar 31, 2025Updated last year