Edgecortix-Inc / mera
A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix
☆32Updated 7 months ago
Alternatives and similar repositories for mera:
Users that are interested in mera are comparing it to the libraries listed below
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆83Updated last year
- EdgeCortix maintained and extended fork of Apache TVM compiler stack utilized by MERA framework. TVM is an open deep learning compiler st…☆11Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆83Updated 8 months ago
- A polyhedral compiler for hardware accelerators☆56Updated 7 months ago
- A Deep Learning Framework for the Posit Number System☆27Updated 7 months ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆33Updated this week
- PyTorch model to RTL flow for low latency inference☆125Updated 11 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- ☆47Updated this week
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆126Updated 3 weeks ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- News and Paper Collections for Machine Learning Hardware☆22Updated 9 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆72Updated last month
- Posit Arithmetic Cores generated with FloPoCo☆24Updated 8 months ago
- AI-ML-NLP Task Group☆13Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by …☆24Updated 4 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆94Updated last year
- ☆16Updated 5 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆102Updated this week
- CGRA framework with vectorization support.☆26Updated this week
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆25Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆100Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- ☆17Updated this week