Alternatives and similar repositories for Basys3

Users that are interested in Basys3 are comparing it to the libraries listed below

• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆141Updated 3 years ago
• nandland / nandland
  All code found on nandland is here. underconstruction.gif
  ☆338Updated 2 years ago
• Digilent / vivado-boards
  ☆447Updated 6 months ago
• jakubcabal / uart-for-fpga
  Simple UART controller for FPGA written in VHDL
  ☆99Updated 3 years ago
• jamieiles / uart
  Verilog UART
  ☆173Updated 12 years ago
• HDLForBeginners / Examples
  ☆95Updated last year
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆503Updated 2 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆179Updated 3 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 3 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆121Updated 6 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆114Updated 4 years ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆175Updated 6 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆296Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆136Updated 6 years ago
• xesscorp / VHDL_Lib
  Library of VHDL components that are useful in larger designs.
  ☆236Updated last year
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆77Updated last year
• Xilinx / XilinxBoardStore
  ☆290Updated last month
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆125Updated 2 years ago
• robertofem / CycloneVSoC-examples
  Examples using the Cyclone V SoC chip
  ☆106Updated 6 years ago
• jakubcabal / spi-fpga
  SPI master and SPI slave for FPGA written in VHDL
  ☆176Updated 4 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆306Updated last year
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆106Updated 4 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆134Updated 10 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆335Updated 8 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago
• ZipCPU / vgasim
  A Video display simulator
  ☆171Updated last month
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆110Updated 8 months ago