Alternatives and similar repositories for CycloneVSoC-examples

Users that are interested in CycloneVSoC-examples are comparing it to the libraries listed below

• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆197Updated 6 years ago
• robseb / rsyocto
  🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone …
  ☆111Updated 3 years ago
• Avnet / hdl
  ☆112Updated 6 months ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆174Updated last year
• ikwzm / FPGA-SoC-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de1…
  ☆166Updated 2 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 2 months ago
• q3k / zturn-stuff
  Migrated to Codeberg
  ☆92Updated 8 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆75Updated 10 months ago
• jakubcabal / uart-for-fpga
  Simple UART controller for FPGA written in VHDL
  ☆103Updated 4 years ago
• imrickysu / ZYNQ-Cookbook
  This is a wiki and code sharing for ZYNQ
  ☆74Updated 9 years ago
• derekmulcahy / xvcpi
  Xilinx Virtual Cable Server for Raspberry Pi
  ☆117Updated 3 years ago
• xesscorp / VHDL_Lib
  Library of VHDL components that are useful in larger designs.
  ☆236Updated last year
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆36Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆118Updated last year
• Digilent / ZYBO
  ☆63Updated 8 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 9 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆311Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆189Updated 2 years ago
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆253Updated 2 months ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆135Updated 2 weeks ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆156Updated 2 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆114Updated 10 months ago
• z4yx / petalinux-docker
  Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)
  ☆121Updated 3 years ago
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆181Updated 3 years ago
• CospanDesign / nysa-sata
  ☆86Updated 8 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆71Updated 3 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆128Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆89Updated 2 years ago