mjlyons / vSPI
Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
☆41Updated 4 months ago
Alternatives and similar repositories for vSPI
Users that are interested in vSPI are comparing it to the libraries listed below
Sorting:
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆62Updated 2 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆55Updated this week
- TCP/IP controlled VPI JTAG Interface.☆65Updated 4 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Verilog Repository for GIT☆32Updated 4 years ago
- Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM☆36Updated last year
- ☆85Updated 8 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- USB 1.1 Host and Function IP core☆22Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆26Updated 6 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago
- Extensible FPGA control platform☆60Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆81Updated 5 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated this week
- Wishbone interconnect utilities☆41Updated 3 months ago
- Open Source ZYNQ Board☆31Updated 9 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- ☆37Updated 4 years ago
- USB 2.0 Device IP Core☆67Updated 7 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- picorv32_soc, simulation env, FPGA, boot code, RTOS☆15Updated 6 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆19Updated 10 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago