jeremybennett / verilator
A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.
☆18Updated 10 years ago
Alternatives and similar repositories for verilator:
Users that are interested in verilator are comparing it to the libraries listed below
- A reconfigurable and extensible VLIW processor implemented in VHDL☆32Updated 10 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- SoCRocket - Core Repository☆35Updated 8 years ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆100Updated 6 years ago
- RISC-V Frontend Server☆62Updated 6 years ago
- Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture☆63Updated 2 years ago
- gdb python scripts for SystemC design introspection and tracing☆32Updated 6 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- The OpenRISC 1000 architectural simulator☆74Updated 7 months ago
- A time-predictable processor for mixed-criticality systems☆58Updated 4 months ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated 2 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated last month
- Parallel Array of Simple Cores. Multicore processor.☆95Updated 5 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- A C to verilog compiler☆52Updated 9 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆116Updated 2 years ago
- ☆45Updated last week
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Hardware Verification library for C++, SystemC and SystemVerilog☆29Updated 12 years ago