Alternatives and similar repositories for verilator:

Users that are interested in verilator are comparing it to the libraries listed below

• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆32Updated 10 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆32Updated 6 years ago
• gem5-gpu / gem5
  Fork of gem5 with a gem5-gpu specific branch. See gem5.org for more information.
  ☆12Updated 7 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆35Updated 8 years ago
• aeste / aemb
  Multi-threaded 32-bit embedded core family.
  ☆24Updated 12 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆97Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• yansyaf / cmake-verilog-vhdl-fpga-template
  CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target
  ☆21Updated last year
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 6 months ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆35Updated last month
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆57Updated 4 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆39Updated 9 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 4 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆76Updated 4 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 8 months ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆74Updated 8 months ago
• jbush001 / NyuziToolchain
  Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture
  ☆63Updated 2 years ago
• Minres / DBT-RISE-RISCV
  An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
  ☆35Updated 6 months ago