Alternatives and similar repositories for cheriot-sail

Users that are interested in cheriot-sail are comparing it to the libraries listed below

• CHERIoT-Platform / cheriot-rtos
  The RTOS components for the CHERIoT research platform
  ☆151Updated last week
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated last month
• au-ts / lionsos
  A secure, fast, and adaptable OS based on the seL4 microkernel
  ☆146Updated this week
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆72Updated this week
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆32Updated last week
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆59Updated this week
• sifiveinc / wake
  The SiFive wake build tool
  ☆91Updated 2 weeks ago
• au-ts / sddf
  A collection of interfaces, libraries and tools for writing device drivers for seL4 that allow accessing devices securely and with low ov…
  ☆36Updated this week
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆79Updated last week
• shacron / sled
  Sled System Emulator
  ☆28Updated 5 months ago
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆81Updated this week
• lucypa / sDDF
  seL4 Device Driver Framework
  ☆21Updated last year
• seL4 / microkit
  Microkit - A simple operating system framework for the seL4 microkernel
  ☆136Updated last week
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆58Updated 2 weeks ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆48Updated last year
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆64Updated 2 months ago
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆45Updated last week
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆88Updated 3 months ago
• fwsGonzo / bigassm
  Assemble 128-bit RISC-V
  ☆46Updated last year
• oxidecomputer / cobalt
  A collection of common Bluespec interfaces/modules.
  ☆102Updated last year
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated last month
• jowinter / dmacu
  Minimal CPU Emulator Powered by the ARM PL080 DMA Controller
  ☆36Updated last year
• qualcomm / eld
  Embedded Linker
  ☆207Updated last week
• betrusted-io / betrusted-soc
  Betrusted main SoC design
  ☆146Updated 2 months ago
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆57Updated last week
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆28Updated last month
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 5 months ago
• emsec / arm-fault-simulator
  ☆33Updated 2 years ago