Alternatives and similar repositories for cheriot-sail:

Users that are interested in cheriot-sail are comparing it to the libraries listed below

• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆100Updated last week
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆58Updated 2 weeks ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆28Updated this week
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆70Updated this week
• CHERIoT-Platform / cheriot-rtos
  The RTOS components for the CHERIoT research platform
  ☆138Updated this week
• au-ts / sddf
  A collection of interfaces, libraries and tools for writing device drivers for seL4 that allow accessing devices securely and with low ov…
  ☆30Updated this week
• lowRISC / manticore
  ☆16Updated 2 years ago
• shacron / sled
  Sled System Emulator
  ☆28Updated last month
• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆35Updated 3 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated last week
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆19Updated 5 years ago
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆37Updated this week
• stefanpie / sa-placer
  ☆14Updated last year
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆26Updated this week
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 4 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 2 weeks ago
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆56Updated last week
• betrusted-io / xous-book
  Documentation on the Xous operating system
  ☆31Updated 8 months ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆77Updated last month
• CTSRD-CHERI / cherios
  CheriOS -- a minimal microkernel that demonstrates "clean-slate" CHERI memory protection and object capabilities
  ☆40Updated 2 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆45Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• oxidecomputer / cobalt
  A collection of common Bluespec interfaces/modules.
  ☆97Updated 11 months ago
• westerndigitalcorporation / sweet-b
  Sweet B is a safe, compact, embeddable library for elliptic curve cryptography.
  ☆35Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆41Updated this week
• YoWASP / nextpnr
  Unofficial nextpnr WebAssembly packages
  ☆16Updated this week
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 9 months ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆39Updated 2 years ago