AXLEproject / axle-zsim-nvmainLinks
This is a fork of zsim (see https://github.com/s5z/zsim) which integrates the NVMain main memory simulator, adding 3D stacking and non-volatile memory support.
☆26Updated 10 years ago
Alternatives and similar repositories for axle-zsim-nvmain
Users that are interested in axle-zsim-nvmain are comparing it to the libraries listed below
Sorting:
- SHMA: Software-managed Caching for Hybrid DRAM/NVM Memory Architectures, implemented with zsim and nvmain hybrid simulators☆63Updated 8 years ago
- This is a processing-in-memory simulator which models 3D-stacked memory within gem5. Also includes the workloads used for IMPICA (In-Memo…☆48Updated 8 years ago
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆212Updated 2 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- gem5-nvmain hybrid simulator supporting simulation of DRAM-NVM hybrid memory system☆79Updated 6 years ago
- A fast and scalable x86-64 multicore simulator☆31Updated 4 years ago
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆178Updated 3 years ago
- gem5 Tips & Tricks☆70Updated 5 years ago
- NVMain - An Architectural Level Main Memory Simulator for Emerging Non-Volatile Memories☆93Updated 6 years ago
- Examples of DPU programs using the UPMEM DPU SDK☆45Updated 10 months ago
- ☆67Updated 8 years ago
- PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is dev…☆163Updated last year
- ☆69Updated 4 years ago
- ☆20Updated 3 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Updated 7 years ago
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆81Updated 3 months ago
- Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.☆192Updated 3 years ago
- DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is inte…☆84Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- Graph accelerator on FPGAs and ASICs☆11Updated 7 years ago
- Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory☆17Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆206Updated 5 years ago
- ☆29Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- ☆107Updated last year
- Cost Model☆19Updated 8 months ago
- ☆10Updated 3 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆182Updated last year
- This repository contains an extended version of SMCSim (originally by Erfan Azarkhish), used for near-data-processing research by Jiwon C…☆14Updated 5 years ago