Alternatives and similar repositories for MIPS-Processor-in-Verilog

Users that are interested in MIPS-Processor-in-Verilog are comparing it to the libraries listed below

• FPGADude / Digital-Design
  Verilog HDL files
  ☆146Updated last year
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆78Updated last year
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆134Updated last month
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆137Updated 6 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆115Updated 4 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆159Updated 2 months ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆132Updated last year
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆137Updated 3 years ago
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆20Updated 2 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆259Updated last month
• iamrk-vlsi / RISC-V-MYTH-Workshop
  5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !
  ☆12Updated 3 years ago
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 2 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆441Updated last month
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆192Updated 3 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆152Updated 10 months ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆111Updated 3 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 3 months ago
• aklsh / getting-started-with-verilog
  Verilog modules for beginners
  ☆28Updated 3 years ago
• mhyousefi / MIPS-pipeline-processor
  A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
  ☆158Updated 3 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆132Updated 5 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆110Updated last month
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆43Updated 6 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆59Updated 8 months ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆32Updated last year
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆29Updated 3 years ago
• raysalemi / Python4RTLVerification
  ☆161Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆50Updated last year
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆31Updated 8 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆104Updated 2 months ago