Marco-Winzker / NN_RGB_FPGA
FPGA Design of a Neural Network for Color Detection
☆75Updated 3 months ago
Alternatives and similar repositories for NN_RGB_FPGA
Users that are interested in NN_RGB_FPGA are comparing it to the libraries listed below
Sorting:
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆108Updated 5 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 6 months ago
- Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …☆34Updated last year
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆102Updated 5 years ago
- UVM and System Verilog Manuals☆41Updated 6 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆61Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆76Updated last year
- Image Processing Toolbox in Verilog using Basys3 FPGA☆198Updated last year
- Implementation of CNN using Verilog☆211Updated 7 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆84Updated 6 years ago
- Basic RISC-V Test SoC☆122Updated 6 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- ☆55Updated 10 months ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆67Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆53Updated 4 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 7 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆150Updated 10 months ago
- A simple implementation of a UART modem in Verilog.☆133Updated 3 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- RISC-V Integration for PYNQ☆172Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- A convolutional neural network implemented in hardware (verilog)☆157Updated 7 years ago
- A 2D convolution hardware implementation written in Verilog☆45Updated 4 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆147Updated 4 years ago
- A Single Cycle Risc-V 32 bit CPU☆45Updated 2 years ago