erbanhun / ZTE_DPDLinks
☆11Updated 7 years ago
Alternatives and similar repositories for ZTE_DPD
Users that are interested in ZTE_DPD are comparing it to the libraries listed below
Sorting:
- LMS sound filtering by Verilog☆43Updated 5 years ago
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆14Updated 9 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- Fractional interpolation using a Farrow structure☆10Updated 2 years ago
- FIR filter implementation☆29Updated 5 years ago
- 基于Verilog实现的全数字锁相环☆41Updated 4 years ago
- FPGA Technology Exchange Group相关文件管理☆54Updated last month
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆18Updated 4 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆53Updated 4 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆29Updated 5 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆48Updated 9 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆60Updated 3 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆69Updated 4 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆33Updated 4 years ago
- configurable cordic core in verilog☆53Updated 11 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆81Updated last year
- A dual-camera based on OminiVison 5460 for GoWin GW2A-55K Combat Board☆33Updated 4 years ago
- 《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆132Updated 2 weeks ago
- FFT implementation using CORDIC algorithm written in Verilog.☆34Updated 7 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆71Updated last month
- A digital phase-locked loop implemented on Spartan-6☆13Updated 7 years ago
- FPGA implementation of pose detection with Kalman filter. (verilog)☆36Updated 3 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆37Updated last year
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆61Updated 6 years ago
- verilog☆21Updated 2 years ago
- An AXI DDR3 SDRAM controller for FPGA☆42Updated last year
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 6 years ago
- FIR implemention with Verilog☆50Updated 6 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆48Updated last year
- This is xc7z020clg400 FPGA hardware core board design☆64Updated 2 years ago