Alternatives and similar repositories for venus:

Users that are interested in venus are comparing it to the libraries listed below

• ThaumicMekanism / venus
  RISC-V instruction set simulator built for education
  ☆155Updated 2 years ago
• hm-riscv / vscode-riscv-venus
  VS Code extension with the Venus RISC-V simulator
  ☆70Updated 6 months ago
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆194Updated 2 years ago
• sequencer / zaozi
  The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project
  ☆26Updated this week
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆199Updated 4 years ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆113Updated 4 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated 6 months ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆145Updated 2 years ago
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆190Updated this week
• riscv-software-src / riscof
  ☆72Updated 4 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆88Updated 11 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated last week
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆49Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆170Updated this week
• rhysd / riscv32-cpu-chisel
  Learning how to make RISC-V 32bit CPU with Chisel
  ☆65Updated 3 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆36Updated this week
• ysyx-org / jemu-decoder
  The decoder library for jemu execution and web documentation
  ☆54Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆138Updated this week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆142Updated last year
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆18Updated last week
• plctlab / plct-toolbox
  PLCT工具箱
  ☆30Updated 2 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆142Updated 7 months ago
• ksco / chibicc-riscv
  A fork of chibicc ported to RISC-V assembly.
  ☆38Updated 2 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 6 months ago
• yamak / axi-nodes
  ☆19Updated 2 years ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated 10 months ago