Alternatives and similar repositories for chibicc-riscv:

Users that are interested in chibicc-riscv are comparing it to the libraries listed below

• ksco / rvemu
  A simple and fast RISC-V JIT emulator.
  ☆131Updated 6 months ago
• siriusdemon / Rare
  Build your own Riscv Emulator in Rust.
  ☆105Updated 2 years ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆86Updated last year
• fmash16 / riscv_emulator
  A basic working RISCV emulator written in C
  ☆64Updated last year
• hellollvm / nanpanjiang-project
  由HelloLLVM社区主席邱吉博士发起，联合HelloGCC等技术社区，推出了「南盘江计划」，致力于帮助更多的女性工程师在编译等基础软件领域实现个人职业目标。
  ☆29Updated last year
• michaelengel / xv6-d1
  Port of MIT's xv6 OS to the Nezha RISC-V board with Allwinner D1 SoC
  ☆104Updated 2 years ago
• ksco / rvld
  Learn how to write a minimal working linker from scratch
  ☆101Updated 9 months ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• HUST-OS / xv6-k210
  Port XV6 to K210 board!
  ☆134Updated 3 years ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated 2 months ago
• space-mit / riscv-ime-extension-spec
  Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…
  ☆51Updated 6 months ago
• pleasewhy / startos
  rewrite subset of linux 2.6 by OOP, C++ advanced topics
  ☆11Updated 3 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆199Updated 4 years ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆19Updated 4 years ago
• ysyx-org / jemu-decoder
  The decoder library for jemu execution and web documentation
  ☆54Updated last year
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆49Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• plctlab / plct-qemu
  PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。
  ☆28Updated 6 months ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆111Updated 3 months ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆48Updated 3 years ago
• rhysd / riscv32-cpu-chisel
  Learning how to make RISC-V 32bit CPU with Chisel
  ☆65Updated 3 years ago
• KuangjuX / hypocaust
  hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
  ☆47Updated 2 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆45Updated 3 weeks ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 11 months ago
• jiegec / kb
  My knowledge base
  ☆42Updated last week
• NJU-ProjectN / i386-manual
  Intel 80386 Reference Programmer's Manual
  ☆64Updated last month
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆75Updated this week
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆174Updated 10 months ago
• js2xxx / umi
  An RISC-V experimental OS
  ☆25Updated last year