jiegec / blog-sourceLinks
The source of my blog.
☆42Updated this week
Alternatives and similar repositories for blog-source
Users that are interested in blog-source are comparing it to the libraries listed below
Sorting:
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆117Updated 10 months ago
- Online judge server for Verilog | verilogoj.ustc.edu.cn☆81Updated last year
- PLCT工具箱☆32Updated 3 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 10 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆174Updated 4 years ago
- The decoder library for jemu execution and web documentation☆54Updated last year
- 可移植的 RISC-V 解释执行模拟器。模拟了常见的SoC外设,支持运行主线Linux。A portable RISC-V emulator working in instruction-interpreting way. Common SoC peripherals ar…☆93Updated 11 months ago
- 一生一芯的信息发布和内容网站☆132Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆24Updated 2 weeks ago
- 龙芯杯21个人赛作品☆35Updated 3 years ago
- ☆53Updated last week
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Updated 2 years ago
- An exquisite superscalar RV32GC processor.☆160Updated 8 months ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Updated 3 years ago
- My knowledge base☆66Updated this week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- ☆20Updated last year
- ☆156Updated last week
- CQU Dual Issue Machine☆37Updated last year
- ☆35Updated 6 years ago
- NJU Virtual Board☆289Updated last week
- Unofficial guide for ysyx students applying to ShanghaiTech University☆22Updated 6 months ago
- Documentation for XiangShan Design☆30Updated this week
- ☆290Updated 2 weeks ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- 重庆大学硬件综合设计课程实验文档☆39Updated last month
- 适用于龙芯杯团队赛入门选手的应急cache模块☆29Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆143Updated last year
- Modern co-simulation framework for RISC-V CPUs☆153Updated this week