Alternatives and similar repositories for yatcpu

Users that are interested in yatcpu are comparing it to the libraries listed below

• SYSU-SCC / yatcpu-docs
  Documentation for YatCPU
  ☆53Updated 2 years ago
• hrpccs / 2022-fall-yatcpu-repo
  ☆24Updated 2 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• vickiegpt / computer-architecture-revisit-a-quantitative-approach
  This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…
  ☆29Updated 2 weeks ago
• CMU-SAFARI / Virtuoso
  Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…
  ☆80Updated 2 months ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆45Updated 2 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆36Updated 4 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• Synthesys-Lab / assassyn
  Asynchronous semantics for architectural simulation and synthesis.
  ☆64Updated this week
• TrivialCompiler / TrivialCompiler
  A toy compiler written in C++17 that translates SysY (a C-like toy language) into ARM-v7a assembly.
  ☆146Updated 4 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆13Updated 4 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆45Updated 2 years ago
• alexshuang / write-your-own-ai-compiler
  《自己动手写AI编译器》
  ☆32Updated last year
• Nelson-Cheung / yatsenos-riscv
  Rebuild YatSenOS On RISC-V 64.
  ☆22Updated 4 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆206Updated 5 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆51Updated 3 weeks ago
• ustb-owl / MimiC
  MimiC is a compiler of C subset (extended SysY language) by USTB NSCSCC team.
  ☆62Updated 2 years ago
• hellollvm / nanpanjiang-project
  由HelloLLVM社区主席邱吉博士发起，联合HelloGCC等技术社区，推出了「南盘江计划」，致力于帮助更多的女性工程师在编译等基础软件领域实现个人职业目标。
  ☆39Updated 6 months ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆52Updated 4 years ago
• gilgamsh / GenshinCPU
  Our repository for NSCSCC
  ☆19Updated 10 months ago
• JamesAslan / MicroArchBench
  ☆76Updated last year
• XpuOS / xsched
  A scheduling framework for multitasking over diverse XPUs, including GPUs, NPUs, ASICs, and FPGAs
  ☆150Updated last week
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆46Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆119Updated last year
• THU-DSP-LAB / llvm-project
  LLVM OpenCL C compiler suite for ventus GPGPU
  ☆58Updated 3 weeks ago