☆89Aug 6, 2024Updated 2 years ago
Alternatives and similar repositories for Toolbox
Users that are interested in Toolbox are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆140Sep 2, 2023Updated 3 years ago
- Schoko Computer☆11Jun 7, 2023Updated 3 years ago
- TinyBasic interpreted by custom microcoded CPU☆13Oct 26, 2026Updated last week
- A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.☆13Jul 24, 2026Updated 3 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆11Sep 13, 2020Updated 6 years ago
- RTL Interview Questions☆12Mar 23, 2019Updated 7 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆30Jul 10, 2024Updated 2 years ago
- IHP Open source SG13G2 Tape Out on May 2025 [Testfield T588] PDK repository☆15May 21, 2025Updated last year
- ☆25Jun 23, 2024Updated 2 years ago
- ☆15Dec 19, 2025Updated 10 months ago
- An open-source DIY, NE555-based analogue synthesizer - play notes with a stylus☆32Oct 24, 2025Updated last year
- ☆22Mar 30, 2023Updated 3 years ago
- DAPLink (CMSIS-DAP) porting to WCH CH32V003 using ch32fun and rv003usb☆15Oct 17, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Sinclair ZX81 schematics (kicad)☆13Aug 25, 2019Updated 7 years ago
- ☆18Aug 14, 2026Updated 2 months ago
- Simple WCH MCU tool to flash over usb (compatible with WCH CH569 & CH565)☆24Jan 28, 2026Updated 9 months ago
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆29Mar 3, 2026Updated 8 months ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆25Dec 11, 2023Updated 2 years ago
- TinyTapeout demo pcb's RP2040 functionality☆27Sep 8, 2026Updated last month
- 100G Udp Link For axi Stream☆17Jun 27, 2023Updated 3 years ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆35Oct 12, 2026Updated 3 weeks ago
- ☆13Mar 25, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆20Jul 5, 2023Updated 3 years ago
- 8 bit CPU optimized for the constraints of tinytapeout☆12Sep 21, 2022Updated 4 years ago
- M.2 PCIe Artix 7 FPGA Accelerator Card☆42Mar 17, 2025Updated last year
- Python code examples for SIGLENT gear☆21Oct 16, 2022Updated 4 years ago
- ☆50Apr 1, 2026Updated 7 months ago
- Verilog ADC interface for adc128s022 found in De0 Nano☆16Jul 7, 2015Updated 11 years ago
- Open-source implementation of the IEEE 1722 protocol, for streaming audio/video, tunneling CAN/LIN messages and enabling remote access to…☆86Oct 26, 2026Updated last week
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- I2C Master Verilog module☆38Jun 1, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- An example Windows 10 UMDF driver for the sole purpose of sending MMIO to BAR regions of an FPGA☆21May 4, 2018Updated 8 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆35May 17, 2020Updated 6 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 8 months ago
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆29Sep 4, 2025Updated last year
- Amaranth HDL libary for building USB-capable SoC designs.☆31Oct 31, 2025Updated last year
- Trying to get a new skill☆39Dec 31, 2024Updated last year
- RTL Design and Implementation of High Performance Algorithm Logic Units☆16Oct 1, 2019Updated 7 years ago