Artificial Neural Network on Altera DE2
☆35Oct 8, 2015Updated 10 years ago
Alternatives and similar repositories for altera-de2-ann
Users that are interested in altera-de2-ann are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Voice Recognition using FPGA-Based Neural Networks☆15Jul 6, 2016Updated 9 years ago
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆29Feb 4, 2017Updated 9 years ago
- Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL☆13Jun 22, 2016Updated 9 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Feb 12, 2018Updated 8 years ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Record something with .md file☆13Jan 23, 2024Updated 2 years ago
- SystemVerilog、Verilog、UVM☆16Jun 23, 2020Updated 5 years ago
- Arline Quantum is an open-source library providing basic functionality for creating and manipulating quantum circuits. It also contains a…☆16Jan 1, 2024Updated 2 years ago
- Documentation source for Sawtooth Lake. Published docs at the link.☆10Feb 8, 2017Updated 9 years ago
- A Verilog parser for Haskell.☆36Jul 6, 2021Updated 4 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- ☆15Feb 25, 2017Updated 9 years ago
- A data acquisition framework in Python and Verilog.☆44Updated this week
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- aiml的C++实现,支持中文,改自libaiml☆16Dec 2, 2012Updated 13 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆23May 11, 2021Updated 4 years ago
- Reference implementations of the GIMLI permutation☆15Jul 9, 2017Updated 8 years ago
- ☆10Oct 6, 2015Updated 10 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17May 30, 2013Updated 12 years ago
- A VHDL implementation of SipHash☆13Feb 19, 2015Updated 11 years ago
- DroidPad Android application☆17Apr 12, 2014Updated 12 years ago
- 观云网盘搜索服务,现支持百度网盘搜索☆11Jul 27, 2015Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Example code for the startKIT developer board☆23Dec 11, 2014Updated 11 years ago
- Hand written number classification done in hardware (De1-SoC board) using neural networks☆25Mar 21, 2018Updated 8 years ago
- Bitstream Fault Analysis Tool☆15Jul 17, 2023Updated 2 years ago
- A DDS core written in VHDL.☆11Jan 5, 2019Updated 7 years ago
- Fast Fourier Transformation Implementation☆14Oct 15, 2012Updated 13 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Rebar3 plugin to interact with Nix ecosystem☆14Jan 11, 2022Updated 4 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- ☆11Sep 13, 2025Updated 7 months ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 6 years ago
- Single-source shortest paths accelerated with AWS F1 FPGA☆14May 2, 2018Updated 7 years ago
- typecho1.2版本已支持文章左右预览,本项目停止维护☆12Dec 28, 2015Updated 10 years ago
- This project is a High and Low pass filter designer written in Octave to design and calculate the filter coefficients for a windows sinc …☆15May 3, 2015Updated 10 years ago
- A batch (multiple concurrent sequence pairs) implementation of Dynamic Time Warping (DTW) in Theano☆10Sep 13, 2015Updated 10 years ago
- A repository of IPs for hardware computer vision (FPGA)☆97Oct 21, 2015Updated 10 years ago
- Implementations of differentiable stacks, queues, and deques from "Learning to Transduce with Unbounded Memory"☆20Sep 8, 2015Updated 10 years ago