A curated list of Deep Learning hardware, cycle/memory optimisation techniques
☆44Aug 9, 2016Updated 9 years ago
Alternatives and similar repositories for awesome-deep-computation
Users that are interested in awesome-deep-computation are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 10 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆13Feb 22, 2018Updated 8 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 9 years ago
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated last month
- DyRACT Open Source Repository☆16May 4, 2016Updated 10 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆49Aug 31, 2017Updated 8 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 8 years ago
- CNN accelerator☆29Jun 11, 2017Updated 8 years ago
- Network on Chip for MPSoC☆28Apr 19, 2026Updated 2 weeks ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 months ago
- Github page for SSDFA☆11Jan 28, 2020Updated 6 years ago
- ChipTools is a utility to automate FPGA build and verification☆26Oct 22, 2021Updated 4 years ago
- ☆12Jul 31, 2017Updated 8 years ago
- ☆16Jun 26, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆21Jul 28, 2016Updated 9 years ago
- SteamVR, only use VIVE Tracker☆21Mar 4, 2019Updated 7 years ago
- CaffePresso: An Optimized Library for Deep Learning on Embedded Accelerator-based platforms☆88Oct 16, 2024Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆20Apr 17, 2016Updated 10 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆30Feb 6, 2023Updated 3 years ago
- An FPGA NES emulator designed by a high level synthesis (HLS)☆16Jun 11, 2017Updated 8 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- Verilog language support in Atom☆18Jun 30, 2019Updated 6 years ago
- A regularly updated comparison of CNN architectures in terms of accuracy, operations and model size☆45Jan 23, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Export GPT2 full inference loop to the single ONNX graph.☆19May 4, 2022Updated 4 years ago
- A simple and naive WPF appliation that launches SSH daemon inside WSL☆11Jun 5, 2019Updated 6 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs (FPGA'17)☆313Nov 16, 2020Updated 5 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆21Feb 12, 2018Updated 8 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 7 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- A formalization of the RVWMO (RISC-V) memory model☆37Jun 23, 2022Updated 3 years ago
- Repository with torchserve examples☆18Oct 6, 2021Updated 4 years ago
- Data Flow Matrix Machines. Generalization of recurrent neural networks.☆15Dec 24, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Ristretto: Quantization and compression of large AI models. Author: Philipp Gysel.☆288Jan 24, 2026Updated 3 months ago
- Code for reproducing key results in the paper "Neural Shuffle-Exchange Networks - Sequence Processing in O(n log n) Time" by Kārlis Freiv…☆11Apr 10, 2020Updated 6 years ago
- implementing a Recurrent Neural Network with binarized weight format on FPGA☆22Sep 3, 2017Updated 8 years ago
- Residual networks with MatConvNet☆24Feb 6, 2016Updated 10 years ago
- Enigma in FPGA☆29May 18, 2019Updated 6 years ago
- ☆14Jul 28, 2016Updated 9 years ago
- Demitasse: SPMD Programing Implementation of Deep Neural Network Library for Mobile Devices(NeurIPS2016WS)☆23Feb 17, 2017Updated 9 years ago