LLM-aided Hardware Design and Verification
☆44Oct 17, 2026Updated this week
Alternatives and similar repositories for GUIDE
Users that are interested in GUIDE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LintLLM is an open-source Verilog linting framework powered by Large Language Models (LLMs).☆12Aug 14, 2026Updated 2 months ago
- ☆17Mar 23, 2026Updated 7 months ago
- ☆15Jul 25, 2024Updated 2 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆45Apr 3, 2025Updated last year
- ☆10Nov 20, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆15Jan 17, 2025Updated last year
- This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augment…☆14Mar 24, 2025Updated last year
- Working space for free software licenses for hardware description language (e.g. VHDL, Verilog, Bluespec) projects☆15Aug 11, 2011Updated 15 years ago
- A curated, community-maintained list of ML/LLM research and tools for integrated-circuit design — across the full flow.☆26Aug 4, 2026Updated 2 months ago
- AMIQ Externally Controlled Test Bench☆12Jan 13, 2025Updated last year
- ☆17Feb 9, 2022Updated 4 years ago
- Generative Benchmark for LLM-Aided Hardware Design☆30Jun 4, 2025Updated last year
- [ICCAD 2025] Squant☆17Jul 3, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- Hack@DAC 2021☆21Jul 24, 2024Updated 2 years ago
- This repository contains 4000 vulnerable hardware designs. Currently this is in Jsonl format for directly using it for fine-tuning LLMs. …☆24Mar 25, 2025Updated last year
- ☆43Dec 21, 2025Updated 10 months ago
- Logarithmic DAC for AY8913 and SN76489 programmable sound generators (Done as part of Zero To ASIC Analog course)☆11Jun 1, 2024Updated 2 years ago
- A web-based Verilog simulator for designing, running, and visualizing RTL code in-browser.☆15Oct 4, 2025Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆39Updated this week
- ☆17Apr 19, 2026Updated 6 months ago
- A complete open-source design-for-testing (DFT) Solution☆206Aug 30, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆15Jun 27, 2024Updated 2 years ago
- Source code for generating the C implementations of HAWK☆15Jul 4, 2025Updated last year
- ☆18Mar 7, 2019Updated 7 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆20Aug 13, 2018Updated 8 years ago
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆30Jun 9, 2025Updated last year
- Multi-agent inference framework for RTL generation. A Verilog agent and a Python reference-model agent independently propose implementati…☆34Jul 27, 2026Updated 2 months ago
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆14May 16, 2024Updated 2 years ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆25May 20, 2026Updated 5 months ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SVA examples and demonstration☆18Sep 8, 2020Updated 6 years ago
- Drop-in GPU kernel optimizer for PyTorch models, no CUDA or GPU expertise required☆25Jun 7, 2026Updated 4 months ago
- ☆36Mar 31, 2025Updated last year
- ☆23May 12, 2026Updated 5 months ago
- TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection☆23Oct 3, 2023Updated 3 years ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆45Aug 8, 2026Updated 2 months ago
- ☆31Aug 18, 2025Updated last year