xddxdd / zjui-ece385-final
ECE385 Final Project - Raiden Shooter Game - at ZJU-UIUC Institute; w/ 16-bit VGA, Sound and Ethernet
☆13Updated 4 years ago
Alternatives and similar repositories for zjui-ece385-final:
Users that are interested in zjui-ece385-final are comparing it to the libraries listed below
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧,控制DA输出相应正弦信号☆9Updated 5 years ago
- Computational Storage Device based on the open source project OpenSSD.☆19Updated 4 years ago
- hdmi-ts Project☆13Updated 7 years ago
- ☆31Updated last year
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆73Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆48Updated 5 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆11Updated last year
- MIAOW2.0 FPGA implementable design☆12Updated 7 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆26Updated last year
- Advanced Debug Interface☆12Updated last week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- Control a MIPI Camera over I2C☆21Updated 4 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆23Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆44Updated 3 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- FPGA demo for Digilent NEXYS 4 board☆22Updated 5 years ago
- turbo 8051☆28Updated 7 years ago
- ☆39Updated 5 years ago
- SDRAM controller with AXI4 interface☆85Updated 5 years ago
- Hardfloat using chisel3☆17Updated 4 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆16Updated 2 years ago
- verilog/FPGA hardware description for very simple GPU☆17Updated 5 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago