Alternatives and similar repositories for xv6-rv32

Users that are interested in xv6-rv32 are comparing it to the libraries listed below

• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆57Updated 2 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆39Updated 5 years ago
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆145Updated last year
• mausimus / rvcc
  Standalone C compiler for RISC-V and ARM
  ☆96Updated last year
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆52Updated 4 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 7 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago
• regymm / buildroot
  buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"
  ☆26Updated last year
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆20Updated 6 years ago
• archlabo / Frix
  IBM PC Compatible SoC for a commercially available FPGA board
  ☆73Updated 9 years ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆155Updated 2 weeks ago
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆73Updated 2 weeks ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆75Updated this week
• ToNi3141 / RasterIX
  OpenGL 1.x implementation for FPGAs
  ☆110Updated this week
• jaruiz / light8080
  Synthesizable i8080-compatible CPU core.
  ☆26Updated 6 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆35Updated 2 years ago
• alangarf / apple-one
  An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
  ☆149Updated 3 months ago
• michaelengel / xv6-d1
  Port of MIT's xv6 OS to the Nezha RISC-V board with Allwinner D1 SoC
  ☆107Updated 3 years ago
• franzflasch / linux_for_riscv_em
  Scripts to automate building linux images for my emulator riscv_em
  ☆16Updated 2 years ago
• tomverbeure / vexriscv_ocd_blog
  Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
  ☆26Updated 3 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 7 years ago
• jborza / emuriscv
  RISC-V emulator in C
  ☆33Updated 4 years ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆74Updated 11 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆60Updated 5 years ago
• fmash16 / riscv_emulator
  A basic working RISCV emulator written in C
  ☆75Updated last year
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆47Updated 3 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆34Updated 9 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆90Updated 5 years ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆95Updated 5 years ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆102Updated 3 years ago