Alternatives and similar repositories for rvcc

Users that are interested in rvcc are comparing it to the libraries listed below

• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆142Updated last year
• fmash16 / riscv_emulator
  A basic working RISCV emulator written in C
  ☆69Updated last year
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆69Updated this week
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆52Updated 2 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆100Updated 2 years ago
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆55Updated last year
• johnwinans / rvddt
  RISC-V Dynamic Debugging Tool
  ☆47Updated 2 years ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆45Updated last year
• revaldinho / opc
  One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
  ☆82Updated last year
• bobbl / punycc
  Very small self-compiling cross compiler for a subset of C
  ☆11Updated 10 months ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆53Updated 4 years ago
• s-rah / pseudos
  A little risc-v assembly OS that can run DOOM on a QEMU riscv64 Virt
  ☆47Updated last year
• michaelengel / xv6-d1
  Port of MIT's xv6 OS to the Nezha RISC-V board with Allwinner D1 SoC
  ☆104Updated 2 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆50Updated 4 years ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆92Updated 4 years ago
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆57Updated 3 years ago
• cr88192 / bgbtech_btsr1arch
  BtSR1 and BJX2 ISA / CPU Architecture
  ☆27Updated 3 weeks ago
• bit-hack / riscv-vm
  A Small RISC-V Virtual Machine
  ☆80Updated 3 years ago
• openhwgroup / corev-gcc
  ☆26Updated 11 months ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆38Updated 4 years ago
• BrunoLevy / TinyPrograms
  Tiny programs from various sources, for testing softcores
  ☆116Updated 5 months ago
• michaelengel / xv6-rv32
  Port of MIT's xv6 OS to 32 bit RISC V
  ☆38Updated 3 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆44Updated 2 years ago
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆34Updated 3 years ago
• theandrew168 / bronzebeard
  Minimal assembler and ecosystem for bare-metal RISC-V development
  ☆53Updated last year
• fuhsnn / widcc
  Simple C compiler for x86-64 Linux able to build real-world projects including Curl, GCC, Git, PHP, Perl, Python, PostgreSQL etc
  ☆38Updated this week
• jamesbowman / j1
  The J1 CPU
  ☆169Updated 4 years ago
• AZHenley / riscv-parser
  Basis of a RISC-V parser to be used for linters or assemblers.
  ☆48Updated 3 years ago
• fernandotcl / TinyEMU
  Tweaks to Fabrice Bellard's TinyEMU
  ☆131Updated last year
• real-xinu / xinu-stm32
  Xinu OS for STM32
  ☆23Updated last year