teknohog / Xilinx-Serial-MinerLinks
Bitcoin miner for Xilinx FPGAs
☆97Updated 12 years ago
Alternatives and similar repositories for Xilinx-Serial-Miner
Users that are interested in Xilinx-Serial-Miner are comparing it to the libraries listed below
Sorting:
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆173Updated 3 years ago
- A Bitcoin miner for the Zynq chip utilizing the Zedboard.☆107Updated last year
- A completely open source implementation of a Bitcoin Miner for Altera FPGAs. This project hopes to promote the free and open development …☆51Updated 12 years ago
- An open source FPGA miner for Blakecoin☆52Updated 10 years ago
- A litecoin scrypt miner implemented with FPGA on-chip memory.☆289Updated 10 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆79Updated 7 years ago
- A simplified version of an FPGA bitcoin miner☆53Updated 6 years ago
- SQRL FK33 board files, example designs and scripts.☆17Updated 2 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆38Updated last year
- ☆63Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- DUAL Spartan6 Development Platform☆86Updated 7 years ago
- FPGA Development for the parallella☆19Updated 7 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- An Open Source FPGA GroestlCoin Miner☆10Updated 7 years ago
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…☆41Updated 6 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆153Updated 7 years ago
- An Open Source configuration of the Arty platform☆130Updated last year
- Public repository for Litefury & Nitefury☆294Updated last year
- Parallel Array of Simple Cores. Multicore processor.☆100Updated 6 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Generic Logic Interfacing Project☆46Updated 4 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- Documenting the Lattice ECP5 bit-stream format.☆56Updated 2 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆122Updated 2 months ago
- RISC-V CPU for OpenFPGAs, in Icestudio☆92Updated last year
- Yet Another RISC-V Implementation☆96Updated 9 months ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆65Updated 8 years ago
- ☆62Updated 3 years ago