Alternatives and similar repositories for Xilinx-Serial-Miner:

Users that are interested in Xilinx-Serial-Miner are comparing it to the libraries listed below

• unixb0y / SystemVerilogSHA256
  SHA256 in (System-) Verilog / Open Source FPGA Miner
  ☆78Updated 7 years ago
• fpgaminer / Open-Source-FPGA-Bitcoin-Miner
  A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…
  ☆173Updated 3 years ago
• stiggy87 / ZynqBTC
  A Bitcoin miner for the Zynq chip utilizing the Zedboard.
  ☆105Updated last year
• teknohog / Open-Source-FPGA-Bitcoin-Miner
  A completely open source implementation of a Bitcoin Miner for Altera FPGAs. This project hopes to promote the free and open development …
  ☆51Updated 11 years ago
• kramble / FPGA-Blakecoin-Miner
  An open source FPGA miner for Blakecoin
  ☆51Updated 10 years ago
• kramble / FPGA-Litecoin-Miner
  A litecoin scrypt miner implemented with FPGA on-chip memory.
  ☆287Updated 10 years ago
• d953i / SQRL_FK33
  SQRL FK33 board files, example designs and scripts.
  ☆17Updated 2 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆35Updated last year
• secworks / sha512
  Verilog implementation of the SHA-512 hash function.
  ☆38Updated 3 years ago
• 0x2fed / FPGA-GroestlCoin-Miner
  An Open Source FPGA GroestlCoin Miner
  ☆10Updated 7 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆56Updated 4 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆129Updated 2 months ago
• GOOD-Stuff / FPGA-SPI-Flash
  Various projects of SPI loader module for xilinx fpga
  ☆29Updated 4 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆39Updated 9 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆88Updated 3 weeks ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆62Updated 8 years ago
• stremovsky / moneroasic
  Cryptonight Monero Verilog code for ASIC
  ☆20Updated 7 years ago
• Goshik92 / SHA256Hasher
  SHA-256 IP core for ZedBoard (Zynq SoC)
  ☆31Updated 6 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆69Updated 9 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆40Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆87Updated 5 years ago
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆54Updated 4 months ago