Alternatives and similar repositories for ARM-CPU:

Users that are interested in ARM-CPU are comparing it to the libraries listed below

• nxbyte / ARM-LEGv8
  Verilog Implementation of an ARM LEGv8 CPU
  ☆104Updated 6 years ago
• yasnakateb / PipelinedARM
  💎 A 32-bit ARM Processor Implementation in Verilog HDL
  ☆19Updated 3 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆79Updated 4 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆54Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆78Updated last week
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆54Updated this week
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆101Updated 11 months ago
• Michaelvll / RISCV_CPU
  A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
  ☆81Updated 5 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 3 weeks ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆118Updated 9 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆76Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆113Updated 6 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆85Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆111Updated 6 months ago
• OpenXiangShan / nexus-am
  ☆34Updated last week
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆88Updated 6 months ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆87Updated 6 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆143Updated 2 weeks ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆102Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆89Updated 3 weeks ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 7 months ago
• riscv-software-src / riscv-isac
  ☆32Updated 5 months ago
• merledu / SIngle-Cycle-RISC-V-In-Verilog
  This repository contains the verilog code files of Single Cycle RISC-V architecture
  ☆28Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆116Updated 4 years ago
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆77Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆66Updated 2 weeks ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago