Alternatives and similar repositories for ARM-CPU

Users that are interested in ARM-CPU are comparing it to the libraries listed below

• nxbyte / ARM-LEGv8
  Verilog Implementation of an ARM LEGv8 CPU
  ☆113Updated 7 years ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆94Updated 7 years ago
• yasnakateb / PipelinedARM
  💎 A 32-bit ARM Processor Implementation in Verilog HDL
  ☆25Updated 3 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆114Updated last year
• evantandersen / fpga-gpu
  A basic GPU for altera FPGAs
  ☆88Updated 6 years ago
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆92Updated 5 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆77Updated 3 weeks ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated 2 months ago
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆73Updated 6 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 7 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• riscv-software-src / riscv-isac
  ☆33Updated last year
• kcelebi / riscv-assembler
  RISC-V Assembly code assembler package for Python.
  ☆53Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆144Updated 3 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆105Updated 9 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 2 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• OpenXiangShan / nexus-am
  ☆42Updated last week
• ashishrana160796 / verilog-starter-tutorials
  Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
  ☆61Updated 5 years ago
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆83Updated 6 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆134Updated 4 months ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆73Updated 4 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆63Updated 2 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆64Updated 6 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆135Updated 7 years ago