Alternatives and similar repositories for ARM-CPU

Users that are interested in ARM-CPU are comparing it to the libraries listed below

• nxbyte / ARM-LEGv8
  Verilog Implementation of an ARM LEGv8 CPU
  ☆106Updated 6 years ago
• yasnakateb / PipelinedARM
  💎 A 32-bit ARM Processor Implementation in Verilog HDL
  ☆19Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆83Updated this week
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆91Updated 2 weeks ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆102Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆56Updated 3 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆46Updated last year
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆82Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆80Updated 2 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆55Updated 3 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆80Updated 4 years ago
• barbedo / verilog-book
  Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
  ☆21Updated 6 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆73Updated 3 years ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆59Updated 3 years ago
• merledu / SIngle-Cycle-RISC-V-In-Verilog
  This repository contains the verilog code files of Single Cycle RISC-V architecture
  ☆30Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 7 months ago
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆79Updated 4 years ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆30Updated 5 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆51Updated 5 years ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆89Updated 7 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆92Updated this week
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆80Updated 4 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆152Updated this week
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆92Updated 5 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆121Updated 10 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 10 months ago