tomverbeure / yosys_gatemapLinks
An example that shows how to map a design to a custom cell library.
☆12Updated 2 years ago
Alternatives and similar repositories for yosys_gatemap
Users that are interested in yosys_gatemap are comparing it to the libraries listed below
Sorting:
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 3 weeks ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated 2 months ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- ☆14Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆38Updated 6 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- ☆34Updated 4 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- ☆22Updated 3 weeks ago
- ☆33Updated 2 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆21Updated this week
- Small footprint and configurable HyperBus core☆12Updated 2 years ago
- AXI Formal Verification IP☆20Updated 4 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated last week
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- ☆39Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Open Source AES☆31Updated last year
- Chisel Examples for the iCESugar FPGA Board☆11Updated 4 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- ☆36Updated 2 years ago
- ☆22Updated 3 years ago
- ☆50Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago