the-aerospace-corporation / satcat5Links
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
☆465Updated last month
Alternatives and similar repositories for satcat5
Users that are interested in satcat5 are comparing it to the libraries listed below
Sorting:
- A configurable RTL to bitstream FPGA toolchain☆43Updated this week
- UPduino 3.0: new 4 layer layout, various other improvements☆342Updated 7 months ago
- FPGA 101 lessons/labs☆390Updated last year
- An attempt to recreate the RP2040 PIO in an FPGA☆303Updated last year
- Small footprint and configurable Ethernet core☆259Updated 2 weeks ago
- List of FPGA Lattice boards using open tools☆332Updated 2 months ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆140Updated 5 months ago
- VHDL synthesis (based on ghdl)☆346Updated 3 months ago
- A modern and open-source cross-platform software for chips reverse engineering.☆266Updated 9 months ago
- Documenting Lattice's 28nm FPGA parts☆144Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆426Updated this week
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆222Updated last year
- WIP 100BASE-TX PHY☆76Updated 9 months ago
- Bluetooth PHY based on one-bit input and output☆231Updated 4 years ago
- ECP5 breakout board in a feather physical format☆505Updated 10 months ago
- How to set up Xilinx Vivado for source control☆107Updated last year
- LiteX boards files☆429Updated last week
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆675Updated 3 years ago
- Multi-platform nightly builds of open source FPGA tools☆299Updated 3 years ago
- 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).☆200Updated last week
- A tutorial for using nmigen☆311Updated 4 years ago
- Public repository for Litefury & Nitefury☆300Updated last year
- PCB for ULX3S FPGA R&D board☆404Updated 4 months ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆675Updated this week
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆587Updated this week
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆725Updated 7 months ago
- 3-stage RV32IMACZb* processor with debug☆927Updated this week
- Small footprint and configurable DRAM core☆435Updated 2 months ago
- Public repository for PicoEVB (Xilinx Artix XC7A50T based)☆259Updated 3 years ago
- VRoom! RISC-V CPU☆510Updated last year