hexdae / toolchains_riscv_gnuLinks
RISC-V bazel toolchains for GCC compilation
☆13Updated last year
Alternatives and similar repositories for toolchains_riscv_gnu
Users that are interested in toolchains_riscv_gnu are comparing it to the libraries listed below
Sorting:
- Bazel rules for Xilinx Vivado☆20Updated 3 years ago
- ☆20Updated 2 weeks ago
- PCB tooling by Diode Computers, Inc.☆164Updated this week
- ARM embedded toolchains for Bazel☆142Updated last month
- Tools for embedded/bare-metal development using bazel☆112Updated last year
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆151Updated last month
- Hardware-In-the-Loop (HiL ⛰️) for high-quality validation 🧪 everywhere 🚀☆27Updated 8 months ago
- ☆12Updated last year
- Bazel/Build Analysis and Navigation Tool☆27Updated last month
- Verilog package manager written in Rust☆143Updated last year
- bazel rules for building mbed-os embedded binaries☆21Updated 2 weeks ago
- Better Boards, Faster! Python-defined circuits with Claude Code as your intelligent design partner☆71Updated 3 weeks ago
- FOSS Flow For FPGA☆423Updated last year
- ☆87Updated last week
- Docker image generation for Xilinx Petalinux Tools☆40Updated 4 months ago
- Open source AMD Xilinx Kria UltraScale+ SoM baseboard☆65Updated last year
- A SystemVerilog Language Server☆194Updated 2 months ago
- Open Source NFC contact card☆29Updated last year
- ☆12Updated 8 months ago
- Docker installation of Vivado tooling☆34Updated 5 months ago
- Rasbperry pi bazel cross compile rules☆49Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆282Updated last year
- The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the deve…☆59Updated last year
- Open-source software-defined EDA☆31Updated last year
- ASIC implementation flow infrastructure, successor to OpenLane☆268Updated this week
- VCD viewer☆100Updated 4 months ago
- A work-in-progress board-level hardware description language (HDL) providing design automation through generators and block polymorphism.☆86Updated last week
- This repository contains Design files for Various Base board Designed for Avnet Zynq Ultrascale+ FPGA SOC☆23Updated 7 months ago
- Open Source 4k CSI-2 Rx core for Xilinx FPGAs☆407Updated 7 years ago
- Bazel build rules for compiling Verilog☆21Updated last year