Alternatives and similar repositories for mmuart:

Users that are interested in mmuart are comparing it to the libraries listed below

• freecores / wb_builder
  WISHBONE Builder
  ☆14Updated 8 years ago
• freecores / ps2
  PS2 interface
  ☆18Updated 7 years ago
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• ClusterM / clujtag-client
  Client for JTAG programmer for AVR microcontrollers
  ☆15Updated last year
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆20Updated 7 years ago
• Digilent / Arty-A7-35-XADC
  ☆19Updated 4 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• mithro / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆17Updated 5 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆17Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• RHSResearchLLC / xvcd
  Xilinx Virtual Cable Daemon
  ☆19Updated 5 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆24Updated 3 years ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 3 weeks ago
• wd5gnr / verifla
  Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
  ☆33Updated 6 years ago
• linuxbest / ahci_mpi
  an sata controller using smallest resource.
  ☆15Updated 11 years ago
• antmicro / ecp5-dc-scm
  Experimental Lattice ECP5-driven Data Center Security Communication Module
  ☆21Updated 8 months ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆29Updated 4 years ago
• ECP5-PCIe / ECP5-Utils
  Utilities for the ECP5 FPGA
  ☆18Updated 3 years ago
• freecores / usb_phy
  USB 1.1 PHY
  ☆10Updated 10 years ago
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆18Updated 5 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆29Updated last year
• cyrozap / python-boundary-scan-tools
  Python tools to interact with boundary scan-capable devices. Useful for reverse engineering, testing, etc.
  ☆16Updated 8 years ago
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated last week
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆26Updated 3 years ago