freecores / mmuart
Simple RS232 UART
☆12Updated 8 years ago
Alternatives and similar repositories for mmuart:
Users that are interested in mmuart are comparing it to the libraries listed below
- WISHBONE Builder☆14Updated 8 years ago
- PS2 interface☆17Updated 7 years ago
- Client for JTAG programmer for AVR microcontrollers☆14Updated last year
- Ethernet MAC 10/100 Mbps☆25Updated 3 years ago
- USB 1.1 Device IP Core☆18Updated 7 years ago
- ☆18Updated 4 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- Freecores website☆19Updated 8 years ago
- USB Full-Speed core written in migen/LiteX☆17Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆28Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- WCH CH569 SerDes Reverse Engineering☆26Updated 2 years ago
- CRUVI Standard Specifications☆17Updated 9 months ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- Control a MIPI Camera over I2C☆21Updated 4 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆23Updated 3 years ago
- Sigma-Delta Analog to Digital Converter in FPGA (VHDL)☆15Updated 7 years ago
- Time to Digital Converter (TDC)☆30Updated 4 years ago
- Simplified environment for litex☆14Updated 4 years ago
- SD device emulator from ProjectVault☆15Updated 5 years ago
- Program Lattice MachXO2/3 with CircuitPython☆12Updated 5 years ago
- Bit streams forthe Ulx3s ECP5 device☆16Updated last year
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- Xilinx Virtual Cable Daemon☆19Updated 5 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 4 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago