Alternatives and similar repositories for openmz

Users that are interested in openmz are comparing it to the libraries listed below

• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆25Updated last year
• antmicro / rowhammer-tester
  ☆64Updated 3 months ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 10 months ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 4 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆55Updated last month
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆44Updated last month
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆111Updated 3 weeks ago
• mageec / beebs
  A set of benchmarks chosen to show the energy consumption of embedded devices under different conditions
  ☆68Updated 2 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆20Updated 4 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆107Updated this week
• ESCristiano / BUSted
  BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
  ☆11Updated last year
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆59Updated 9 months ago
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆45Updated this week
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 3 months ago
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆46Updated 2 weeks ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆35Updated 3 weeks ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 months ago
• ekiwi / icesugar-chisel
  Chisel Examples for the iCESugar FPGA Board
  ☆12Updated 4 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 3 weeks ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated this week
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• hex-five / multizone-fpga
  This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…
  ☆31Updated last year
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆69Updated 4 months ago