lp6m / VexRiscv_Ultra96

Related projects ⓘ

Alternatives and complementary repositories for VexRiscv_Ultra96

• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• rits-drsl / ZybotR2-96-fpt19
  An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
  ☆17Updated 4 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆35Updated 2 months ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 4 years ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 2 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆34Updated last week
• fixstars / ultra96_design
  Repository of HW design and SW for Ultra96 board + MIPI board
  ☆17Updated 5 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆128Updated last year
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆25Updated 3 years ago
• FPGA-Research-Manchester / fos
  FOS - FPGA Operating System
  ☆62Updated 4 years ago
• HirokiNakahara / FPGA_lecture
  Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
  ☆26Updated 3 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆152Updated 2 months ago
• Digilent / Petalinux-Zybo-Z7-20
  ☆52Updated 2 years ago
• Xilinx / Xilinx_Kria_KV260_Workshop
  ☆40Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆102Updated last week
• ryuz / jelly
  Original FPGA platform
  ☆51Updated last week
• pulp-platform / pulp-dsp
  ☆32Updated last year
• Digilent / digilent-vivado-scripts
  ☆63Updated 4 months ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆79Updated 3 months ago
• Xilinx / logicnets
  ☆83Updated 5 months ago
• verilator / example-systemverilog
  ☆34Updated 9 months ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆92Updated 3 months ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated 6 months ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last week
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆44Updated 5 months ago
• HirokiNakahara / FPGA_AI_Edge_Contest_2019
  Sample scripts for FPGA-based AI Edge Contest 2019
  ☆11Updated 4 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆25Updated 6 months ago