Alternatives and similar repositories for VexRiscv_Ultra96:

Users that are interested in VexRiscv_Ultra96 are comparing it to the libraries listed below

• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆26Updated 4 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆36Updated last month
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• Digilent / Petalinux-Zybo-Z7-20
  ☆53Updated 2 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆130Updated last year
• rits-drsl / ZybotR2-96-fpt19
  An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
  ☆17Updated 4 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆37Updated 3 months ago
• fixstars / ultra96_design
  Repository of HW design and SW for Ultra96 board + MIPI board
  ☆17Updated 6 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 4 years ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 2 years ago
• ryuz / jelly
  Original FPGA platform
  ☆62Updated this week
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆50Updated 5 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆69Updated 3 years ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 4 years ago
• Xilinx / kria-vitis-platforms
  Kria Vitis platforms and overlays
  ☆96Updated 2 weeks ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆154Updated 3 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆64Updated last month
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆46Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• Xilinx / Xilinx_Kria_KV260_Workshop
  ☆43Updated 3 years ago
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆85Updated 2 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated last month
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 5 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 4 months ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆27Updated 4 months ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆66Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago